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authorMartin Roth <martinroth@google.com>2017-11-02 13:13:54 -0600
committerMartin Roth <martinroth@google.com>2017-11-03 21:54:39 +0000
commit42ac3073300091bbce4024a5d072c700b870383a (patch)
tree4f3503c64b0bc7f13b013ff4c6d8ccbb3569cabb
parent5bb0d755669765f93d8f3483667476ca14b96585 (diff)
downloadcoreboot-42ac3073300091bbce4024a5d072c700b870383a.tar.xz
vendorcode/amd/pi/00670F00: remove unused headers
These header files are not used, so remove them. BUG=b:68812513 TEST=Build Change-Id: Ib43fc544186f7b46ecf9b318b9edcf008f2d08dc Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/22298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat
-rw-r--r--src/vendorcode/amd/pi/00670F00/Dispatcher.h51
-rw-r--r--src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h222
-rw-r--r--src/vendorcode/amd/pi/00670F00/Include/Options.h68
-rw-r--r--src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h137
-rw-r--r--src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h213
-rw-r--r--src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h1045
-rw-r--r--src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h200
7 files changed, 0 insertions, 1936 deletions
diff --git a/src/vendorcode/amd/pi/00670F00/Dispatcher.h b/src/vendorcode/amd/pi/00670F00/Dispatcher.h
deleted file mode 100644
index 7ec23607ec..0000000000
--- a/src/vendorcode/amd/pi/00670F00/Dispatcher.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD Pushhigh Interface
- *
- * Contains interface to Pushhigh entry
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Legacy
- * @e \$Revision$ @e \$Date$
- *
- */
- /*****************************************************************************
- *
- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _DISPATCHER_H_
-#define _DISPATCHER_H_
-
-// AGESA function prototypes
-AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
-AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
-
-#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h b/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h
deleted file mode 100644
index 683ed64618..0000000000
--- a/src/vendorcode/amd/pi/00670F00/Include/GeneralServices.h
+++ /dev/null
@@ -1,222 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * General Services
- *
- * Provides Services similar to the external General Services API, except
- * suited to use within AGESA components. Socket, Core and PCI identification.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Common
- * @e \$Revision$ @e \$Date$
- *
- */
- /*****************************************************************************
- *
- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _GENERAL_SERVICES_H_
-#define _GENERAL_SERVICES_H_
-
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-#define NUMBER_OF_EVENT_DATA_PARAMS 4
-
-/**
- * AMD Device id for MMIO check.
- */
-#define AMD_DEV_VEN_ID 0x1022
-#define AMD_DEV_VEN_ID_ADDRESS 0
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * An AGESA Event Log entry.
- */
-typedef struct {
- AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
- UINT32 EventInfo; ///< Uniquely identifies the event.
- UINT32 DataParam1; ///< Event specific additional data
- UINT32 DataParam2; ///< Event specific additional data
- UINT32 DataParam3; ///< Event specific additional data
- UINT32 DataParam4; ///< Event specific additional data
-} AGESA_EVENT;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-/**
- * Get a specified Core's APIC ID.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[in] Socket The Core's Socket.
- * @param[in] Core The Core id.
- * @param[out] ApicAddress The Core's APIC ID.
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval TRUE The core is present, APIC Id valid
- * @retval FALSE The core is not present, APIC Id not valid.
- */
-BOOLEAN
-GetApicId (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 Socket,
- IN UINT32 Core,
- OUT UINT8 *ApicAddress,
- OUT AGESA_STATUS *AgesaStatus
-);
-
-/**
- * Get Processor Module's PCI Config Space address.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[in] Socket The Core's Socket.
- * @param[in] Module The Module in that Processor
- * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- * @retval TRUE The core is present, PCI Address valid
- * @retval FALSE The core is not present, PCI Address not valid.
- */
-BOOLEAN
-GetPciAddress (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN UINT32 Socket,
- IN UINT32 Module,
- OUT PCI_ADDR *PciAddress,
- OUT AGESA_STATUS *AgesaStatus
-);
-
-/**
- * "Who am I" for the current running core.
- *
- * @param[in] StdHeader Header for library and services.
- * @param[out] Socket The current Core's Socket
- * @param[out] Module The current Core's Processor Module
- * @param[out] Core The current Core's core id.
- * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
- *
- */
-VOID
-IdentifyCore (
- IN AMD_CONFIG_PARAMS *StdHeader,
- OUT UINT32 *Socket,
- OUT UINT32 *Module,
- OUT UINT32 *Core,
- OUT AGESA_STATUS *AgesaStatus
-);
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * Is this the BSP core?
- *
- * @param[in,out] StdHeader Header for library and services
- *
- * @retval TRUE Is BSP core
- * @retval FALSE Is not BSP Core
- *
- */
-BOOLEAN
-IsBsp (
- IN OUT AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function logs AGESA events into the event log.
- */
-VOID
-PutEventLog (
- IN AGESA_STATUS EventClass,
- IN UINT32 EventInfo,
- IN UINT32 DataParam1,
- IN UINT32 DataParam2,
- IN UINT32 DataParam3,
- IN UINT32 DataParam4,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function gets event logs from the circular buffer.
- */
-AGESA_STATUS
-GetEventLog (
- OUT AGESA_EVENT *EventRecord,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/**
- * This function gets event logs from the circular buffer without flushing the entry.
- */
-BOOLEAN
-PeekEventLog (
- OUT AGESA_EVENT *EventRecord,
- IN UINT16 Index,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- * This routine programs the registers necessary to get the PCI MMIO mechanism
- * up and functioning.
- */
-VOID
-InitializePciMmio (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/*---------------------------------------------------------------------------------------*/
-/**
- *
- * Is it SecureS3
- *
- * @param[in] StdHeader Header for library and services
- *
- * @retval TRUE It's SecureS3
- * @retval FALSE It's NOT SecureS3
- *
- */
-BOOLEAN
-IsSecureS3 (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-#endif // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/pi/00670F00/Include/Options.h b/src/vendorcode/amd/pi/00670F00/Include/Options.h
deleted file mode 100644
index 4bd67439aa..0000000000
--- a/src/vendorcode/amd/pi/00670F00/Include/Options.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AGESA options structures
- *
- * Contains options control structures for the AGESA build options
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: Core
- * @e \$Revision$ @e \$Date$
- */
- /*****************************************************************************
- *
- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-
-#ifndef _OPTIONS_H_
-#define _OPTIONS_H_
-
-/**
- * Provide topology limits for loops and runtime, based on supported families.
- */
-typedef struct {
- UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
- ///< supported families and other build options.
- UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
- ///< on supported families.
-} OPTIONS_CONFIG_TOPOLOGY;
-
-/**
- * Dispatch Table.
- *
- * The push high dispatcher uses this table to find what entries are currently in the build image.
- */
-typedef struct {
- UINT32 FunctionId; ///< The function id specified.
- IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
-} DISPATCH_TABLE;
-
-
-#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h
deleted file mode 100644
index 87077ce805..0000000000
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/Feature/cpuCacheInit.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Execution Cache Allocation functions.
- *
- * Contains code for doing Execution Cache Allocation for ROM space
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision$ @e \$Date$
- *
- */
- /*****************************************************************************
- *
- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _CPU_CACHE_INIT_H_
-#define _CPU_CACHE_INIT_H_
-
-/*----------------------------------------------------------------------------
- * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
- *
- *----------------------------------------------------------------------------
- */
-
-/*-----------------------------------------------------------------------------
- * DEFINITIONS AND MACROS
- *
- *-----------------------------------------------------------------------------
- */
-#define BSP_STACK_SIZE_64K 65536
-#define BSP_STACK_SIZE_32K 32768
-
-#define CORE0_STACK_SIZE 16384
-#define CORE1_STACK_SIZE 4096
-
-#define AMD_MTRR_FIX4K_BASE 0x268
-#define AMD_MTRR_VARIABLE_BASE6 0x20C
-#define AMD_MTRR_VARIABLE_BASE7 0x20E
-
-#define WP_IO 0x0505050505050505ull
-
-#define AGESA_CACHE_SIZE_REDUCED 1
-#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
-#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
-#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
-#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
-#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
-#define AGESA_DEALLOCATE_CACHE_REGIONS 7
-
-/*----------------------------------------------------------------------------
- * TYPEDEFS, STRUCTURES, ENUMS
- *
- *----------------------------------------------------------------------------
- */
-/// Cache-As-Ram Executable region allocation modes
-typedef enum {
- LimitedByL2Size, ///< Execution space must be allocated from L2
- InfiniteExe, ///< Family can support unlimited Execution space
- MaxCarExeMode ///< Used as limit or bounds check
-} CAR_EXE_MODE;
-
-/// Cache Information
-typedef struct {
- IN UINT32 BspStackSize; ///< Stack size of BSP
- IN UINT32 Core0StackSize; ///< Stack size of primary cores
- IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
- IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
- IN UINT32 SharedMemSize; ///< Shared memory size
- IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
- IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
- IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
- IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
-} CACHE_INFO;
-
-/// Merged memory region overlap type
-typedef enum {
- EmptySet, ///< One of the regions is zero length
- Disjoint, ///< The two regions do not touch
- Adjacent, ///< one region is next to the other, no gap
- CommonEnd, ///< regions overlap with a common end point
- Extending, ///< the 2nd region is extending the size of the 1st
- Contained, ///< the 2nd region is wholely contained inside the 1st
- CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
- Identity, ///< the two regions are the same
- CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
- NotCombinable ///< the combined regions do not follow the cache block rules
-} OVERLAP_TYPE;
-
-/// Result of merging two memory regions for cache coverage
-typedef struct {
- IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
- IN OUT UINT32 MergedSize; ///< Size of the merged regions
- OUT UINT32 OverlapAmount; ///< the size of the overlapping section
- OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
-} MERGED_CACHE_REGION;
-
-/*----------------------------------------------------------------------------
- * FUNCTIONS PROTOTYPE
- *
- *----------------------------------------------------------------------------
- */
-AGESA_STATUS
-AllocateExecutionCache (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
- );
-
-#endif // _CPU_CACHE_INIT_H_
-
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h
deleted file mode 100644
index 418fb2f6d2..0000000000
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuEarlyInit.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Reset API, and related functions and structures.
- *
- * Contains code that initialized the CPU after early reset.
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision$ @e \$Date$
- *
- */
- /*****************************************************************************
- *
- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _CPU_EARLY_INIT_H_
-#define _CPU_EARLY_INIT_H_
-
-
-/*---------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *---------------------------------------------------------------------------------------
- */
-AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
-
-/*---------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *---------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
-#define LOW_NODE_DEVICEID 24
-#define NB_CAPABILITIES 0xE8 //Function 3 Registers
-//----------------------------------------------------------------------------
-// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/* All lengths are in bytes */
-#define MICROCODE_TRIADE_SIZE 28
-#define MICROCODE_HEADER_LENGTH 64
-
-/**
- * @page ucodeflag Microcode Patches Signature Guide
- *
- * We mark patches in the ROM with a signature so that they can be easily found
- *
- * @anchor Microcode Patch Signature
- * @li @e Microcode Patch Signature @n
- * Microcode patches are marked by adding a signature before patches in the ROM image to
- * help identify where they are located.
- * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
- * The other is '$UCODE4K', it indicates there's a following patch with 4K size.
- * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
- *
- *
- */
-/// Microcode patch flag for replacement
-typedef struct {
- IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
-} MICROCODE_PATCHES_FLAG;
-
-#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
-#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
-#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
-
-/* Offsets in UCODE PATCH Header */
-/* Note: Header is 64 bytes */
-#define DATE_CODE_OFFSET 0 // 4 bytes
-#define PATCH_ID 4 // 4 bytes
-#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
-#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
-#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
-#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
-#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
-#define PROCESSOR_REV_ID 24 // 2 bytes
-#define CHIPSET_1_REV_ID 26 // 1 byte
-#define CHIPSET_2_REV_ID 27 // 1 byte
-
-/*---------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *---------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// A structure representing BrandId[15:0] from
-/// CPUID Fn8000_0001_EBX
-typedef struct {
- UINT8 String1:4; ///< An index to a string value used to create the name string
- UINT8 String2:4; ///< An index to a string value used to create the name string
- UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
- UINT8 Model:7; ///< A field used to create the model number in the name string
- UINT8 Socket:4; ///< Specifies the package type
- UINT8 Cores:4; ///< Identifies how many physical cores are present
-} AMD_CPU_BRAND_DATA;
-
-/// A structure containing string1 and string2 values
-/// as well as information pertaining to their usage
-typedef struct {
- IN UINT8 Cores; ///< Appropriate number of physical cores
- IN UINT8 Page; ///< This string's page number
- IN UINT8 Index; ///< String index
- IN UINT8 Socket; ///< Package type information
- IN CONST CHAR8 *Stringstart; ///< The literal string
- IN UINT8 Stringlength; ///< Number of characters in the string
-} AMD_CPU_BRAND;
-
-/// An entire CPU brand table.
-typedef struct {
- UINT8 NumberOfEntries; ///< The number of entries in the table.
- CONST AMD_CPU_BRAND *Table; ///< The table entries.
-} CPU_BRAND_TABLE;
-
-/**
- * Set down core register
- *
- * @CpuServiceInstances
- *
- * @param[in] FamilySpecificServices The current Family Specific Services.
- * @param[in] Socket Socket ID.
- * @param[in] Module Module ID in socket.
- * @param[in] LeveledCores Number of core.
- * @param[in] CoreLevelMode Core level mode.
- * @param[in] StdHeader Header for library and services.
- *
- * @retval TRUE Down Core register is updated.
- * @retval FALSE Down Core register is not updated.
- */
-typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
- IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
- IN UINT32 *Socket,
- IN UINT32 *Module,
- IN UINT32 *LeveledCores,
- IN CORE_LEVELING_TYPE CoreLevelMode,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Reference to a method
-typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
-
-/**
- * Provide the interface to the Core Leveling Family Specific Services.
- *
- * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
- * Each supported Family must provide an implementation for all methods in this interface, even if the
- * implementation is a CommonReturn().
- */
-struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
- UINT16 Revision; ///< Interface version
- // Public Methods.
- PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
-};
-
-/*---------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *---------------------------------------------------------------------------------------
- */
-
-// These are P U B L I C functions, used by IBVs
-AGESA_STATUS
-AmdCpuEarly (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- );
-
-// These are P U B L I C functions, used by AGESA
-AGESA_STATUS
-PmInitializationAtEarly (
- IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-AmdCpuEarlyInitializer (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
- );
-
-#endif // _CPU_EARLY_INIT_H_
-
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h
deleted file mode 100644
index 04bd01334d..0000000000
--- a/src/vendorcode/amd/pi/00670F00/Proc/CPU/cpuLateInit.h
+++ /dev/null
@@ -1,1045 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * AMD CPU Late Init API functions Prototypes.
- *
- * Contains code for doing any late CPU initialization
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: CPU
- * @e \$Revision$ @e \$Date$
- *
- */
- /*****************************************************************************
- *
- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#ifndef _CPU_LATE_INIT_H_
-#define _CPU_LATE_INIT_H_
-
-#include "Filecode.h"
-
-// Forward declaration needed for multi-structure mutual references.
-AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
-/*----------------------------------------------------------------------------------------
- * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
- *----------------------------------------------------------------------------------------
- */
-
-/*----------------------------------------------------------------------------------------
- * D E F I N I T I O N S A N D M A C R O S
- *----------------------------------------------------------------------------------------
- */
-
-//----------------------------------------------------------------------------
-// DMI DEFINITIONS AND MACROS
-//
-//----------------------------------------------------------------------------
-#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
-// SMBIOS constant definition
-#define CENTRAL_PROCESSOR 0x03
-#define EXTERNAL_CLOCK_DFLT 200
-#define EXTERNAL_CLOCK_100MHZ 100
-#define P_FAMILY_UNKNOWN 0x02
-#define P_ENGINEERING_SAMPLE 0x00
-#define P_CHARACTERISTICS 0x4
-#define CACHE_CFG_L1 0x180
-#define CACHE_CFG_L2 0x181
-#define CACHE_CFG_L3 0x182
-#define SRAM_TYPE 0x10
-#define ERR_CORRECT_TYPE 0x06
-#define CACHE_TYPE 0x05
-#define DMI_ASSOCIATIVE_OTHER 0x01
-#define DMI_ASSOCIATIVE_UNKNOWN 0x02
-#define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03
-#define DMI_ASSOCIATIVE_2_WAY 0x04
-#define DMI_ASSOCIATIVE_4_WAY 0x05
-#define DMI_ASSOCIATIVE_FULLY 0x06
-#define DMI_ASSOCIATIVE_8_WAY 0x07
-#define DMI_ASSOCIATIVE_16_WAY 0x08
-#define DMI_ASSOCIATIVE_12_WAY 0x09
-#define DMI_ASSOCIATIVE_24_WAY 0x0A
-#define DMI_ASSOCIATIVE_32_WAY 0x0B
-#define DMI_ASSOCIATIVE_48_WAY 0x0C
-#define DMI_ASSOCIATIVE_64_WAY 0x0D
-#define DMI_ASSOCIATIVE_20_WAY 0x0E
-#define SOCKET_POPULATED 0x40
-#define CPU_STATUS_UNKNOWN 0x00
-#define CPU_STATUS_ENABLED 0x01
-
-// Processor Upgrade Definition
-#define P_UPGRADE_UNKNOWN 0x02
-#define P_UPGRADE_NONE 0x06
-
-//----------------------------------------------------------------------------
-// CDIT DEFINITIONS AND MACROS
-//
-//----------------------------------------------------------------------------
-#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer
-
-
-//----------------------------------------------------------------------------
-// P-STATE DEFINITIONS AND MACROS
-//
-//----------------------------------------------------------------------------
-//-------------------------------------
-// ERROR Codes
-//-------------------------------------
-#define NO_ERROR 0x0
-#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation
-#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match
-#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW!
-#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch
-#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size
-#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available
-#define NO_PSS_ENTRY 0x0FFFFul
-#define INVALID_FREQ 0x0FFFFFFFFul
-
-//-------------------------
-// Default definitions
-// AMD BKDG default values
-//-------------------------
-#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS
-#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV
-#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV
-#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop
-#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS
-#define DEFAULT_PLL_LOCK_TIME 2 // 2uS
-#define DEFAULT_TRANSITION_LATENCY 100 // 100uS
-#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS
-#define DEFAULT_CPU_SCOPE_NUMBER "0UPC"
-
-// Defines for Common ACPI
-// -----------------------------
-#define SCOPE_OPCODE 0x10
-#define NAME_OPCODE 0x08
-#define METHOD_OPCODE 0x14
-#define PACKAGE_OPCODE 0x12
-#define BUFFER_OPCODE 0x11
-#define BYTE_PREFIX_OPCODE 0x0A
-#define WORD_PREFIX_OPCODE 0x0B
-#define DWORD_PREFIX_OPCODE 0x0C
-#define RETURN_OPCODE 0xA4
-#define ACPI_BUFFER 0x080A0B11ul
-
-// Generic Register Descriptor (GDR) Fields
-#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID
-#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size
-
-// Defines for ACPI Scope Table
-// ----------------------------
-#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \
- PCT_STRUCT_SIZE + \
- PSS_HEADER_STRUCT_SIZE + \
- PSS_BODY_STRUCT_SIZE + \
- PPC_HEADER_BODY_STRUCT_SIZE)
-#define SCOPE_VALUE1 0x5C
-#define SCOPE_VALUE2 0x2E
-#define SCOPE_NAME__ '_'
-#define SCOPE_NAME_P 'P'
-#define SCOPE_NAME_R 'R'
-#define SCOPE_NAME_S 'S'
-#define SCOPE_NAME_B 'B'
-#define SCOPE_NAME_C 'C'
-#define SCOPE_NAME_U 'U'
-#define SCOPE_NAME_0 '0'
-#define SCOPE_NAME_1 '1'
-#define SCOPE_NAME_2 '2'
-#define SCOPE_NAME_3 '3'
-#define SCOPE_NAME_A 'A'
-
-#ifdef OEM_SCOPE_NAME
- #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
- #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
- #endif
- #define SCOPE_NAME_VALUE OEM_SCOPE_NAME
-#else
- #define SCOPE_NAME_VALUE SCOPE_NAME_C
-#endif // OEM_SCOPE_NAME
-
-#ifdef OEM_SCOPE_NAME1
- #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
- ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
- (OEM_SCOPE_NAME1 == '_')))
- #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
- #endif
- #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1
-#else
- #define SCOPE_NAME_VALUE1 SCOPE_NAME_0
-#endif // OEM_SCOPE_NAME
-
-// Defines for PCT Control and Status Table
-// ----------------------------------------
-#define PCT_NAME__ '_'
-#define PCT_NAME_P 'P'
-#define PCT_NAME_C 'C'
-#define PCT_NAME_T 'T'
-#define PCT_VALUE1 0x11022C12ul
-#define PCT_VALUE2 0x0A14
-#define PCT_VALUE3 0x11
-#define GENERIC_REG_DESCRIPTION 0x82
-#define PCT_LENGTH 0x0C
-#define PCT_ADDRESS_SPACE_ID 0x7F
-#define PCT_REGISTER_BIT_WIDTH 0x40
-#define PCT_REGISTER_BIT_OFFSET 0x00
-#define PCT_RESERVED 0x00
-#define PCT_CONTROL_REG_LO 0xC0010062ul
-#define PCT_CONTROL_REG_HI 0x00
-#define PCT_VALUE4 0x14110079ul
-#define PCT_VALUE5 0x110A
-#define PCT_STATUS_REG_LO 0x00
-#define PCT_STATUS_REG_HI 0x00
-#define PCT_VALUE6 0x0079
-
-
-// Defines for PSS Header Table
-// ----------------------------
-#define PSS_NAME__ '_'
-#define PSS_NAME_X 'X'
-#define PSS_NAME_P 'P'
-#define PSS_NAME_S 'S'
-#define PSS_LENGTH (sizeof pssBodyStruct + 3)
-#define NUM_OF_ITEMS_IN_PSS 0x00
-
-
-// Defines for PSS Header Table
-// ----------------------------
-#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1
-#define PSS_NUM_OF_ELEMENTS 0x06
-#define PSS_FREQUENCY 0x00
-#define PSS_POWER 0x00
-#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY
-#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY
-#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
- (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
- (DEFAULT_EXT_TYPE << 27) + \
- (DEFAULT_PLL_LOCK_TIME << 20) + \
- (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
- (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
- (PSS_VID << 6) + PSS_FID)
-#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
-
-// Defines for XPSS Header Table
-// ----------------------------
-#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1
-#define XPSS_NUM_OF_ELEMENTS 0x08
-#define XPSS_ACPI_BUFFER 0x080A0B11ul
-
-
-// Defines for PPC Header Table
-// ----------------------------
-#define PPC_NAME__ '_'
-#define PPC_NAME_P 'P'
-#define PPC_NAME_C 'C'
-#define PPC_NAME_V 'V'
-#define PPC_METHOD_FLAGS 0x00;
-#define PPC_VALUE1 0x0A;
-
-// Defines for PSD Header Table
-// ----------------------------
-#define PSD_NAME__ '_'
-#define PSD_NAME_P 'P'
-#define PSD_NAME_S 'S'
-#define PSD_NAME_D 'D'
-#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2)
-#define PSD_VALUE1 0x01
-
-
-// Defines for PSD Header Table
-// ----------------------------
-#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1)
-#define NUM_OF_ENTRIES 0x05
-#define PSD_NUM_OF_ENTRIES 0x05
-#define PSD_REVISION 0x00
-#define PSD_DEPENDENCY_DOMAIN 0x00
-#define PSD_COORDINATION_TYPE_HW_ALL 0xFE
-#define PSD_COORDINATION_TYPE_SW_ANY 0xFD
-#define PSD_COORDINATION_TYPE_SW_ALL 0xFC
-#define PSD_NUM_OF_PROCESSORS 0x01
-#define PSD_TWO_CORES_PER_COMPUTE_UNIT 0x02
-#define PSD_THREE_CORES_PER_COMPUTE_UNIT 0x03
-#define PSD_FOUR_CORES_PER_COMPUTE_UNIT 0x04
-
-
-#define CUSTOM_PSTATE_FLAG 0x55
-#define PSTATE_FLAG_1 0x55
-#define TARGET_PSTATE_FLAG 0xAA
-#define PSTATE_FLAG_2 0xAA
-
-/*----------------------------------------------------------------------------------------
- * T Y P E D E F S, S T R U C T U R E S, E N U M S
- *----------------------------------------------------------------------------------------
- */
-//----------------------------------------------------------------------------
-// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-
-//--------------------------------------------
-// AML code definition
-// (Scope)
-//---------------------------------------------
-/// SCOPE
-typedef struct _SCOPE {
- UINT8 ScopeOpcode; ///< Opcode
- UINT16 ScopeLength; ///< Scope Length
- UINT8 ScopeValue1; ///< Value1
- UINT8 ScopeValue2; ///< Value2
- UINT8 ScopeNamePt1a__; ///< Name Pointer
- UINT8 ScopeNamePt1a_P; ///< Name Pointer
- UINT8 ScopeNamePt1a_R; ///< Name Pointer
- UINT8 ScopeNamePt1b__; ///< Name Pointer
- UINT8 ScopeNamePt2a_C; ///< Name Pointer
- UINT8 ScopeNamePt2a_P; ///< Name Pointer
- UINT8 ScopeNamePt2a_U; ///< Name Pointer
- UINT8 ScopeNamePt2a_0; ///< Name Pointer
-} SCOPE;
-#define SCOPE_STRUCT_SIZE 13 // 13 Bytes
-
-//--------------------------------------------
-// AML code definition
-// (PCT Header and Body)
-//---------------------------------------------
-
-///Performance Control Header
-typedef struct _PCT_HEADER_BODY {
- UINT8 NameOpcode; ///< Opcode
- UINT8 PctName_a__; ///< String "_"
- UINT8 PctName_a_P; ///< String "P"
- UINT8 PctName_a_C; ///< String "C"
- UINT8 PctName_a_T; ///< String "T"
- UINT32 Value1; ///< Value1
- UINT16 Value2; ///< Value2
- UINT8 Value3; ///< Value3
- UINT8 GenericRegDescription1; ///< Generic Reg Description
- UINT16 Length1; ///< Length1
- UINT8 AddressSpaceId1; ///< PCT Address Space ID
- UINT8 RegisterBitWidth1; ///< PCT Register Bit Width
- UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset
- UINT8 Reserved1; ///< Reserved
- UINT32 ControlRegAddressLo; ///< Control Register Address Low
- UINT32 ControlRegAddressHi; ///< Control Register Address High
- UINT32 Value4; ///< Value4
- UINT16 Value5; ///< Value 5
- UINT8 GenericRegDescription2; ///< Generic Reg Description
- UINT16 Length2; ///< Length2
- UINT8 AddressSpaceId2; ///< PCT Address Space ID
- UINT8 RegisterBitWidth2; ///< PCT Register Bit Width
- UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset
- UINT8 Reserved2; ///< Reserved
- UINT32 StatusRegAddressLo; ///< Control Register Address Low
- UINT32 StatusRegAddressHi; ///< Control Register Address High
- UINT16 Value6; ///< Values
-} PCT_HEADER_BODY;
-#define PCT_STRUCT_SIZE 50 // 50 Bytes
-
-
-//--------------------------------------------
-// AML code definition
-// (PSS Header)
-//--------------------------------------------
-///Performance Supported States Header
-typedef struct _PSS_HEADER {
- UINT8 NameOpcode; ///< Opcode
- UINT8 PssName_a__; ///< String "_"
- UINT8 PssName_a_P; ///< String "P"
- UINT8 PssName_a_S; ///< String "S"
- UINT8 PssName_b_S; ///< String "S"
- UINT8 PkgOpcode; ///< Package Opcode
- UINT16 PssLength; ///< PSS Length
- UINT8 NumOfItemsInPss; ///< Number of Items in PSS
-} PSS_HEADER;
-#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
-
-
-//--------------------------------------------
-// AML code definition
-// (PSS Body)
-//--------------------------------------------
-///Performance Supported States Body
-typedef struct _PSS_BODY {
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PkgLength; ///< Package Length
- UINT8 NumOfElements; ///< Number of Elements
- UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
- UINT32 Frequency; ///< Frequency
- UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
- UINT32 Power; ///< Power
- UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
- UINT32 TransitionLatency; ///< Transition Latency
- UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
- UINT32 BusMasterLatency; ///< Bus Master Latency
- UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5
- UINT32 Control; ///< Control
- UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6
- UINT32 Status; ///< Status
-} PSS_BODY;
-#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes
-
-
-/*--------------------------------------------
- * AML code definition
- * (XPSS Header)
- *--------------------------------------------
- */
-/// Extended PSS Header
-typedef struct _XPSS_HEADER {
- UINT8 NameOpcode; ///< 08h
- UINT8 XpssName_a_X; ///< String "X"
- UINT8 XpssName_a_P; ///< String "P"
- UINT8 XpssName_a_S; ///< String "S"
- UINT8 XpssName_b_S; ///< String "S"
- UINT8 PkgOpcode; ///< 12h
- UINT16 XpssLength; ///< XPSS Length
- UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS
-} XPSS_HEADER;
-#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
-
-/*--------------------------------------------
- * AML code definition
- * (XPSS Body)
- *--------------------------------------------
- */
-/// Extended PSS Body
-typedef struct _XPSS_BODY {
- UINT8 PkgOpcode; ///< 12h
- UINT8 PkgLength; ///< Package Length
- UINT8 XpssValueTbd; ///< XPSS Value
- UINT8 NumOfElements; ///< Number of Elements
- UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
- UINT32 Frequency; ///< Frequency
- UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
- UINT32 Power; ///< Power
- UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
- UINT32 TransitionLatency; ///< Transition Latency
- UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
- UINT32 BusMasterLatency; ///< Bus Master Latency
- UINT32 ControlBuffer; ///< Control Buffer
- UINT32 ControlLo; ///< Control Low
- UINT32 ControlHi; ///< Control High
- UINT32 StatusBuffer; ///< Status Buffer
- UINT32 StatusLo; ///< Status Low
- UINT32 StatusHi; ///< Status High
- UINT32 ControlMaskBuffer; ///< Control Mask Buffer
- UINT32 ControlMaskLo; ///< Control Mask Low
- UINT32 ControlMaskHi; ///< Control Mask High
- UINT32 StatusMaskBuffer; ///< Status Mask Buffer
- UINT32 StatusMaskLo; ///< Status Mask Low
- UINT32 StatusMaskHi; ///< Status Mask High
-} XPSS_BODY;
-#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes
-
-/*--------------------------------------------
- * AML code definition
- * (PPC Header and Body)
- *--------------------------------------------
- */
-/// Performance Present Capabilities Header
-typedef struct _PPC_HEADER_BODY {
- UINT8 NameOpcode; ///< Name Opcode
- UINT8 PpcName_a_P; ///< String "P"
- UINT8 PpcName_b_P; ///< String "P"
- UINT8 PpcName_a_C; ///< String "C"
- UINT8 PpcName_a_V; ///< String "V"
- UINT8 Value1; ///< Value
- UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap
- UINT8 MethodOpcode; ///< Method Opcode
- UINT8 PpcLength; ///< Method Length
- UINT8 PpcName_a__; ///< String "_"
- UINT8 PpcName_c_P; ///< String "P"
- UINT8 PpcName_d_P; ///< String "P"
- UINT8 PpcName_b_C; ///< String "C"
- UINT8 MethodFlags; ///< Method Flags
- UINT8 ReturnOpcode; ///< Return Opcoce
- UINT8 PpcName_e_P; ///< String "P"
- UINT8 PpcName_f_P; ///< String "P"
- UINT8 PpcName_c_C; ///< String "C"
- UINT8 PpcName_b_V; ///< String "V"
-
-} PPC_HEADER_BODY;
-#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes
-#define PPC_METHOD_LENGTH 11 // 11 Bytes
-
-
-/*--------------------------------------------
- * AML code definition
- * (PSD Header)
- *--------------------------------------------
- */
-/// P-State Dependency Header
-typedef struct _PSD_HEADER {
- UINT8 NameOpcode; ///< Name Opcode
- UINT8 PsdName_a__; ///< String "_"
- UINT8 PsdName_a_P; ///< String "P"
- UINT8 PsdName_a_S; ///< String "S"
- UINT8 PsdName_a_D; ///< String "D"
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PsdLength; ///< PSD Length
- UINT8 Value1; ///< Value
-} PSD_HEADER;
-#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes
-
-/*--------------------------------------------
- * AML code definition
- * (PSD Body)
- *--------------------------------------------
- */
-/// P-State Dependency Body
-typedef struct _PSD_BODY {
- UINT8 PkgOpcode; ///< Package Opcode
- UINT8 PkgLength; ///< Package Length
- UINT8 NumOfEntries; ///< Number of Entries
- UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte
- UINT8 PsdNumOfEntries; ///< PSD Number of Entries
- UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte
- UINT8 PsdRevision; ///< PSD Revision
- UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord
- UINT32 DependencyDomain; ///< Dependency Domain
- UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord
- UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
- UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord
- UINT32 NumOfProcessors; ///< Number of Processors
-} PSD_BODY;
-#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes
-
-//----------------------------------------------------------------------------
-// WHEA TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-
-/// HEST MCE TABLE
-typedef struct _AMD_HEST_MCE_TABLE {
- UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure.
- UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into
- UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP).
- UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into
- UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL).
- UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
- UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required
-} AMD_HEST_MCE_TABLE;
-
-/// HEST CMC TABLE
-typedef struct _AMD_HEST_CMC_TABLE {
- UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure.
- UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
- UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required
-} AMD_HEST_CMC_TABLE;
-
-/// HEST BANK
-typedef struct _AMD_HEST_BANK {
- UINT8 BankNum; ///< Zero-based index identifies the machine check error bank.
- UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank
- ///< is to be cleared during system initialization.
- UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
- UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
- ///< modified by the OS. If the bit for the associated parameter is
- ///< set, the parameter is writable by the OS.
- UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero.
-
- UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check
- UINT32 CtrlInitDataMSD; ///< bank's control register
- UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
- UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
- UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
-} AMD_HEST_BANK;
-
-/// Initial data of AMD_HEST_BANK
-typedef struct _AMD_HEST_BANK_INIT_DATA {
- UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD
- UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD
- UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr
- UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr
- UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr
- UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr
-} AMD_HEST_BANK_INIT_DATA;
-
-/// MSR179 Global Machine Check Capabilities data struct
-typedef struct _MSR_MCG_CAP_STRUCT {
- UINT64 Count:8; ///< Indicates the number of
- ///< error-reporting banks visible to each core
- UINT64 McgCtlP:1; ///< 1=The machine check control registers
- UINT64 Rsvd:55; ///< reserved
-} MSR_MCG_CAP_STRUCT;
-
-/// Initial data of WHEA
-typedef struct _AMD_WHEA_INIT_DATA {
- UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine
- UINT32 GlobCapInitDataMSD; ///< Check global capability register
- UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine
- UINT32 GlobCtrlInitDataMSD; ///< Check global control register
- UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check
- ///< bank is to be cleared during system initialization
- UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
- UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
- ///< modified by the OS. If the bit for the associated parameter is
- ///< set, the parameter is writable by the OS.
- UINT8 HestBankNum; ///< Number of HEST Bank
- AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank
-} AMD_WHEA_INIT_DATA;
-
-//----------------------------------------------------------------------------
-// DMI TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// DMI brand information
-typedef struct {
- UINT16 String1:4; ///< String1
- UINT16 String2:4; ///< String2
- UINT16 Model:7; ///< Model
- UINT16 Pg:1; ///< Page
-} BRAND_ID;
-
-/// DMI cache information
-typedef struct {
- UINT32 L1CacheSize; ///< L1 cache size
- UINT8 L1CacheAssoc; ///< L1 cache associativity
- UINT32 L2CacheSize; ///< L2 cache size
- UINT8 L2CacheAssoc; ///< L2 cache associativity
- UINT32 L3CacheSize; ///< L3 cache size
- UINT8 L3CacheAssoc; ///< L3 cache associativity
-} CPU_CACHE_INFO;
-
-/// DMI processor information
-typedef struct {
- UINT8 ExtendedFamily; ///< Extended Family
- UINT8 ExtendedModel; ///< Extended Model
- UINT8 BaseFamily; ///< Base Family
- UINT8 BaseModel; ///< Base Model
- UINT8 Stepping; ///< Stepping
- UINT8 PackageType; ///< PackageType
- BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page
- UINT8 TotalCoreNumber; ///< Number of total cores
- UINT8 EnabledCoreNumber; ///< Number of enabled cores
- UINT8 ProcUpgrade; ///< ProcUpdrade
- CPU_CACHE_INFO CacheInfo; ///< CPU cache info
-} CPU_TYPE_INFO;
-
-/// A structure containing processor name string and
-/// the value that should be provide to DMI type 4 processor family
-typedef struct {
- IN CONST CHAR8 *Stringstart; ///< The literal string
- IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family
-} CPU_T4_PROC_FAMILY;
-
-/// DMI ECC information
-typedef struct {
- BOOLEAN EccCapable; ///< ECC Capable
-} CPU_GET_MEM_INFO;
-
-/* Transfer vectors for DMI family specific routines */
-typedef VOID OPTION_DMI_GET_CPU_INFO (
- IN OUT CPU_TYPE_INFO *CpuInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef VOID OPTION_DMI_GET_PROC_FAMILY (
- IN OUT UINT8 *T4ProcFamily,
- IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
- IN CPU_TYPE_INFO *CpuInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef UINT8 OPTION_DMI_GET_VOLTAGE (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef UINT16 OPTION_DMI_GET_MAX_SPEED (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef UINT16 OPTION_DMI_GET_EXT_CLOCK (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-typedef VOID OPTION_DMI_GET_MEM_INFO (
- IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-/// Brand table entry format
-typedef struct {
- UINT8 PackageType; ///< Package type
- UINT8 PgOfBrandId; ///< Page
- UINT8 NumberOfCores; ///< Number of cores
- UINT8 String1ofBrandId; ///< String1
- UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table
-} DMI_BRAND_ENTRY;
-
-/// Family specific data table structure
-struct _PROC_FAMILY_TABLE {
- UINT64 ProcessorFamily; ///< processor
- OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors
- OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information
- OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage
- OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed
- OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed
- OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information
- UINT8 LenBrandList; ///< size of brand table
- CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier
-};
-
-//----------------------------------------------------------------------------
-// TYPEDEFS, STRUCTURES, ENUMS
-//
-//----------------------------------------------------------------------------
-/// Format for Header
-typedef struct {
- UINT8 Sign[4]; ///< Signature
- UINT32 TableLength; ///< Table Length
- UINT8 Revision; ///< Revision
- UINT8 Checksum; ///< Checksum
- UINT8 OemId[6]; ///< OEM ID
- UINT8 OemTableId[8]; ///< OEM Tabled ID
- UINT32 OemRev; ///< OEM Revision
- UINT8 CreatorId[4]; ///< Creator ID
- UINT32 CreatorRev; ///< Creator Revision
-} ACPI_TABLE_HEADER;
-
-//----------------------------------------------------------------------------
-// CRAT TYPEDEFS, STRUCTURES, ENUMS
-// Component Resource Affinity Table
-//----------------------------------------------------------------------------
-/// Format for CRAT Header
-typedef struct {
- UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table.
- UINT32 Length; ///< Length, in bytes, of the entire CRAT
- UINT8 Revision; ///< 0
- UINT8 Checksum; ///< Entire table must sum to zero.
- UINT8 OemId[6]; ///< OEM ID
- UINT8 OemTableId[8]; ///< OEM Tabled ID
- UINT32 OemRev; ///< OEM Revision
- UINT8 CreatorId[4]; ///< Creator ID
- UINT32 CreatorRev; ///< Creator Revision
- UINT32 TotalEntries; ///< total number[n] of entries in the CRAT
- UINT16 NumDomains; ///< Number of HSA proximity domains
- UINT8 Reserved[6]; ///< Reserved
-} CRAT_HEADER;
-
-/// Flags field of the CRAT HSA Processing Unit Affinity Structure
-typedef struct {
- UINT32 Enabled:1; ///< Enabled
- UINT32 HotPluggable:1; ///< Hot Pluggable
- UINT32 CpuPresent:1; ///< Cpu Present
- UINT32 GpuPresent:1; ///< Gpu Present
- UINT32 IommuPresent:1; ///< IOMMU Present
- UINT32 :27; ///< Reserved
-} CRAT_HSA_PROCESSING_UNIT_FLAG;
-
-/// CRAT HSA Processing Unit Affinity Structure
-typedef struct {
- UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure
- UINT8 Length; ///< 40
- UINT16 Reserved; ///< Reserved
- CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure
- UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
- UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain
- UINT16 NumCPUCores; ///< Indicates count of CCompute execution units present in this APU node.
- UINT16 NumSIMDCores; ///< Indicates maximum count of HCompute SIMD cores present in this node.
- UINT16 MaxWavesSIMD; ///< This identifies the max. number of launched waves per SIMD.
- UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components.
- UINT16 HSACapability; ///< Must be 0
- UINT16 LDSSizeInKB; ///< Size of LDS memory per SIMD Wavefront
- UINT8 WaveFrontSize; ///< 64, may be 32 for some FSA based architectures
- UINT8 NumBanks; ///< Number of Banks or "Shader Engines", typically 1 or 2
- UINT16 uEngineIdentifier; ///< Identifier (Rev) of the GPU uEngine or firmware
- UINT8 NumArrays; ///< Number of SIMD Arrays per Engine
- UINT8 NumCUPerArray; ///< Number of Compute Units (CU) per SIMD Array
- UINT8 NumSIMDPerCU; ///< Number of SIMD representing a Compute Unit
- UINT8 MaxSlotsScratchCU; ///< Max. Number of temp. memory ("scratch") wave slots
- ///< available to access, may be 0 if HW has no restrictions
- UINT8 Reserved1[4]; ///< Reserved
-} CRAT_HSA_PROCESSING_UNIT;
-
-/// Flags field of the CRAT Memory Affinity Structure
-typedef struct {
- UINT32 Enabled:1; ///< Enabled
- UINT32 HotPluggable:1; ///< Hot Pluggable
- UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory
- UINT32 :29; ///< Reserved
-} CRAT_MEMORY_FLAG;
-
-/// CRAT Memory Affinity Structure
-typedef struct {
- UINT8 Type; ///< 1 - CRAT Memory Affinity Structure
- UINT8 Length; ///< 40
- UINT16 Reserved; ///< Reserved
- CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged
- UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
- UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range
- UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range
- UINT32 LengthLow; ///< Low 32Bits of the length of the memory range
- UINT32 LengthHigh; ///< High 32Bits of the length of the memory range
- UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface
- UINT8 Reserved1[8]; ///< Reserved
-} CRAT_MEMORY;
-
-/// Flags field of the CRAT Cache Affinity structure
-typedef struct {
- UINT32 Enabled:1; ///< Enabled
- UINT32 DataCache:1; ///< 1 if cache includes data
- UINT32 InstructionCache:1; ///< 1 if cache includes instructions
- UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality
- UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality
- UINT32 :27; ///< Reserved
-} CRAT_CACHE_FLAG;
-
-/// CRAT Cache Affinity Structure
-typedef struct {
- UINT8 Type; ///< 2 - CRAT Cache Affinity Structure
- UINT8 Length; ///< 64
- UINT16 Reserved; ///< Reserved
- CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled
- UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component
- UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
- UINT32 CacheSize; ///< Cache size in KB
- UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
- UINT8 LinesPerTag; ///< Cache Lines per tag
- UINT16 CacheLineSize; ///< Cache line size in bytes
- UINT8 Associativity; ///< Cache associativity
- ///< The associativity fields are encoded as follows:
- ///< 00h: Reserved.
- ///< 01h: Direct mapped.
- ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
- ///< FFh: Fully associative
- UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded.
- ///< 0: Cache is strictly exclusive to lower level caches.
- ///< 1: Cache is mostly exclusive to lower level caches.
- ///< 2: Cache is strictly inclusive to lower level caches.
- ///< 3: Cache is mostly inclusive to lower level caches.
- ///< 4: Cache is a "constant cache" (= explicit update)
- ///< 5: Cache is a "specialty cache" (e.g. Texture cache)
- ///< 6-7: Reserved
- ///< CacheProperties bits [7:3] are reserved
- UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds.
- UINT8 Reserved1[8]; ///< Reserved
-} CRAT_CACHE;
-
-/// Flags field of the CRAT TLB Affinity structure
-typedef struct {
- UINT32 Enabled:1; ///< Enabled
- UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data.
- UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions.
- UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality
- UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality
- UINT32 TLB4KBase256:1; ///< 1 if value in table is factored by 256 to get number of 4K entries
- UINT32 :1; ///< Reserved
- UINT32 TLB2MBase256:1; ///< 1 if value in table is factored by 256 to get number of 2M entries
- UINT32 :1; ///< Reserved
- UINT32 TLB1GBase256:1; ///< 1 if value in table is factored by 256 to get number of 1G entries
- UINT32 :22; ///< Reserved
-} CRAT_TLB_FLAG;
-
-/// CRAT TLB Affinity Structure
-typedef struct {
- UINT8 Type; ///< 3 - CRAT TLB Affinity Structure
- UINT8 Length; ///< 64
- UINT16 Reserved; ///< Reserved
- CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined
- UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
- UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
- UINT32 TlbLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
- UINT8 DataTlbAssociativity2MB; ///< Data TLB associativity for 2MB pages
- ///< The associativity fields are encoded as follows:
- ///< 00h: Reserved.
- ///< 01h: Direct mapped.
- ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
- ///< FFh: Fully associative.
- UINT8 DataTlbSize2MB; ///< Data TLB number of entries for 2MB.
- UINT8 InstructionTlbAssociativity2MB; ///< Instruction TLB associativity for 2MB pages
- ///< The associativity fields are encoded as follows:
- ///< 00h: Reserved.
- ///< 01h: Direct mapped.
- ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
- ///< FFh: Fully associative.
- UINT8 InstructionTlbSize2MB; ///< Instruction TLB number of entries for 2MB pages.
- UINT8 DataTlbAssociativity4K; ///< Data TLB Associativity for 4KB pages
- UINT8 DataTlbSize4K; ///< Data TLB number of entries for 4KB pages
- UINT8 InstructionTlbAssociativity4K; ///< Instruction TLB Associativity for 4KB pages
- UINT8 InstructionTlbSize4K; ///< Instruction TLB number of entries for 4KB pages
- UINT8 DataTlbAssociativity1G; ///< Data TLB Associativity for 1GB pages
- UINT8 DataTlbSize1G; ///< Data TLB number of entries for 1GB pages
- UINT8 InstructionTlbAssociativity1G; ///< Instruction TLB Associativity for 1GB pages
- UINT8 InstructionTlbSize1G; ///< Instruction TLB number of entries for 1GB pages
- UINT8 Reserved1[4]; ///< Reserved
-} CRAT_TLB;
-
-/// Flags field of the CRAT FPU Affinity structure
-typedef struct {
- UINT32 Enabled:1; ///< Enabled
- UINT32 :31; ///< Reserved
-} CRAT_FPU_FLAG;
-
-/// CRAT FPU Affinity Structure
-typedef struct {
- UINT8 Type; ///< 4 - CRAT FPU Affinity Structure
- UINT8 Length; ///< 64
- UINT16 Reserved; ///< Reserved
- CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined
- UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
- UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
- UINT32 FPUSize; ///< Product specific
- UINT8 Reserved1[16]; ///< Reserved
-} CRAT_FPU;
-
-/// Flags field of the CRAT IO Affinity structure
-typedef struct {
- UINT32 Enabled:1; ///< Enabled
- UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions)
- UINT32 :30; ///< Reserved
-} CRAT_IO_FLAG;
-
-/// CRAT IO Affinity Structure
-typedef struct {
- UINT8 Type; ///< 5 - CRAT IO Affinity Structure
- UINT8 Length; ///< 64
- UINT16 Reserved; ///< Reserved
- CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined.
- UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to
- UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to
- UINT8 IoType; ///< IO Interface type. Values defined are
- ///< 0: Undefined
- ///< 1: Hypertransport
- ///< 2: PCI Express
- ///< 3: Other (e.g. internal)
- ///< 4-255: Reserved
- UINT8 VersionMajor; ///< Major version of the Bus interface
- UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional)
- UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds.
- UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds.
- UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s
- UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s
- UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes
- UINT8 Reserved1[24]; ///< Reserved
-} CRAT_IO;
-
-#define CRAT_MAX_LENGTH 0x800ul ///< Reserve 2K for CRAT
-#define LOW_NODE_DEVICEID 24
-/// CRAT entry type
-typedef enum {
- CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure
- CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure
- CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure
- CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure
- CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure
- CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure
-} CRAT_ENTRY_TYPE;
-
-/*----------------------------------------------------------------------------------------
- * F U N C T I O N P R O T O T Y P E
- *----------------------------------------------------------------------------------------
- */
-
-AGESA_STATUS
-AmdCpuLate (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig
- );
-
-AGESA_STATUS
-CreateAcpiWhea (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN OUT VOID **WheaMcePtr,
- IN OUT VOID **WheaCmcPtr
- );
-
-AGESA_STATUS
-CreateDmiRecords (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN OUT DMI_INFO **DmiTable
- );
-
-AGESA_STATUS
-GetType4Type7Info (
- IN AMD_CONFIG_PARAMS *StdHeader,
- IN DMI_INFO *DmiBufferPtr
- );
-
-VOID
-DmiGetT4ProcFamilyFromBrandId (
- IN OUT UINT8 *T4ProcFamily,
- IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
- IN CPU_TYPE_INFO *CpuInfo,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-VOID
-GetNameString (
- IN OUT CHAR8 *String,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-BOOLEAN
-IsSourceStrContainTargetStr (
- IN OUT CHAR8 *SourceStr,
- IN OUT CONST CHAR8 *TargetStr,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-CreateAcpiCrat (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- OUT VOID **CratPtr
- );
-
-AGESA_STATUS
-CreateAcpiCdit (
- IN OUT AMD_CONFIG_PARAMS *StdHeader,
- IN PLATFORM_CONFIGURATION *PlatformConfig,
- OUT VOID **CditPtr
- );
-
-VOID
-ChecksumAcpiTable (
- IN OUT ACPI_TABLE_HEADER *Table,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-RunLateApTaskOnAllAPs (
- IN AP_EXE_PARAMS *ApParams,
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-AGESA_STATUS
-IdleAllAps (
- IN AMD_CONFIG_PARAMS *StdHeader
- );
-
-UINT32
-InterlockedIncrement (
- IN UINT32 *Value
- );
-
-UINT32
-InterlockedDecrement (
- IN UINT32 *Value
- );
-
-#endif // _CPU_LATE_INIT_H_
diff --git a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h b/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h
deleted file mode 100644
index bca7b5bd59..0000000000
--- a/src/vendorcode/amd/pi/00670F00/Proc/Fch/Kern/KernFch.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/* $NoKeywords:$ */
-/**
- * @file
- *
- * FCH registers definition
- *
- *
- *
- * @xrefitem bom "File Content Label" "Release Content"
- * @e project: AGESA
- * @e sub-project: FCH
- * @e \$Revision$ @e \$Date$
- *
- */
- /*****************************************************************************
- *
- * Copyright (c) 2008 - 2016, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of Advanced Micro Devices, Inc. nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#define KERN_FCH_SATA_DID 0x7900
-#define KERN_FCH_SATA_AHCI_DID 0x7901
-#define KERN_FCH_SATA_AMDAHCI_DID 0x7904
-
-#define KERN_FCH_USB_XHCI_DID 0x7914 // Dev 0x10 Func 0
-#define KERN_FCH_USB_EHCI_DID 0x7908 // Dev 0x12 Func 0
-#define KERN_FCH_SMBUS_DID 0x790B // Dev 0x14 Func 0
-#define KERN_FCH_LPC_DID 0x790E // Dev 0x14 Func 3
-#define KERN_FCH_SD_DID 0x7906 // Dev 0x14 Func 7
-
-#define KERN_EHCI1_BUS_DEV_FUN ((0x12 << 3) + 0)
-#define KERN_EHCI1_BUS 0
-#define KERN_EHCI1_DEV 18
-#define KERN_EHCI1_FUNC 0
-#define KERN_EHCI2_BUS_DEV_FUN ((0x13 << 3) + 0)
-#define KERN_EHCI2_BUS 0
-#define KERN_EHCI2_DEV 19
-#define KERN_EHCI2_FUNC 0
-#define KERN_EHCI3_BUS_DEV_FUN ((0x16 << 3) + 0)
-#define KERN_EHCI3_BUS 0
-#define KERN_EHCI3_DEV 22
-#define KERN_EHCI3_FUNC 0
-
-// Specific FCH register for Kern
-#define FCH_EHCI_REG64 0x64
-#define FCH_EHCI_REGA4 0xA4
-
-// HD Audio/Azalia
-#define KERN_EVENT_HD_AUDIO_MSI_ENABLE 0x02010100ul // HD Audio/Azalia MSI enable.
-#define KERN_EVENT_HD_AUDIO_DISABLE 0x02010101ul // HD Audio/Azalia Disable.
-#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC 0x02010102ul // HD Audio/Azalia Configure CODEC.
-#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC_BUSY 0x02010103ul // HD Audio/Azalia Configure CODEC Reset.
-#define KERN_ERROR_HD_AUDIO_RESET 0x02030100ul // HD Audio/Azalia Reset Failure.
-#define KERN_ERROR_HD_AUDIO_CODEC 0x02030101ul // HD Audio/Azalia Codec Not Found.
-// HW ACPI
-#define KERN_EVENT_HWACPI_PROG_ACPI_PMTBL 0x02010200ul // FCH program ACPI PM Controller Base Address.
-#define KERN_EVENT_HWACPI_PROG_ACPI_MMIO_IN_RESET 0x02010201ul // FCH program ACPIMMIO registers in RESET.
-#define KERN_EVENT_HWACPI_PROG_SCI_MAP 0x02010202ul // FCH program SCI map by OEM table (ACPIMMIO 0xFED803xx).
-#define KERN_EVENT_HWACPI_PROG_GPIO_MAP 0x02010203ul // FCH program GPIO setting by OEM table (ACPIMMIO 0xFED801xx).
-#define KERN_EVENT_HWACPI_PROG_SATA_PHY 0x02010204ul // FCH program SATA PHY by OEM table.
-#define KERN_EVENT_RTC_DAYLIGHT_SAVING_TIME 0x02010205ul // FCH RTC DayLight Saving Workaround.
-#define KERN_EVENT_RTC_CLEAR_BANK_SELECTION 0x02010206ul // FCH RTC clear BankSelection 0x0A Bit4 prevent error.
-#define KERN_EVENT_RTC_WA 0x02010207ul // FCH RTC workaround is set.
-#define KERN_EVENT_KBD_CONNECTED_THRU_USB 0x02010208ul // FCH IRQ1/IRQ12 connected to USB controller.
-#define KERN_EVENT_LEGACY_FREE_SET 0x02010209ul // FCH None Legacy IO setting.
-#define KERN_EVENT_ENABLED_ASF_REMOTE_CTRL 0x0201020Aul // FCH Enable ASF remote control function.
-#define KERN_EVENT_PCIEXP_WAKESTATUS_WA 0x0201020Bul // FCH PciExp Wake Status Workaround.
-#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL_IN_RESET 0x0201020Cul // FCH program OEM/Platform BIOS ACPIMMIO registers.
-#define KERN_EVENT_HWACPI_PROG_MMIOTBL 0x02010200ul // FCH program ACPIMMIO registers. (1st.)
-#define KERN_EVENT_HWACPI_NO_SIOKBC_ENABLE 0x02010201ul // FCH No SIO/KBC function is enabled.
-#define KERN_EVENT_HWACPI_NO_SIOKBC_DISABLE 0x02010202ul // FCH No SIO/KBC function is disabled.
-#define KERN_EVENT_HWACPI_PROG_SPECIFIC_MMIOTBL 0x02010203ul // FCH program Specific ACPIMMIO registers. (2nd.)
-#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL 0x02010204ul // FCH program OEM/Platform BIOS ACPIMMIO registers (3rd.)
-#define KERN_EVENT_HWACPI_SPREAD_SPECTRUM 0x02010205ul // FCH Enable Spread Spectrum function.
-#define KERN_EVENT_HWACPI_INT_CLK_SET 0x02010206ul // FCH Set Intermal Clock Display as 48Mhz.
-#define KERN_EVENT_HPET_TIMER_TICK_INTERVAL_WA_SET 0x02010207ul // FCH HPET timer tick interval workaround is set.
-#define KERN_EVENT_C1E_ENABLE 0x02010208ul // FCH C1e Enabled.
-#define KERN_EVENT_NATIVEPCIE_MODE_SET 0x02010208ul // FCH Native PCIe mode is set.
-#define KERN_ERROR_HPET_TBL_NOT_FOUND 0x02030200ul // FCH HPET Table does not found.
-// HWM
-#define KERN_EVENT_IMC_DISABLE 0x02010300ul // FCH HWM/IMC is disabled.
-#define KERN_EVENT_IMC_ENABLE 0x02010301ul // FCH HWM/IMC is enabled.
-// IMC
-#define KERN_EVENT_IMC_SW_TOGGLE_EVENT 0x02010302ul // FCH IMC Software Toggle Strapping. (IMC statement change)
-#define KERN_EVENT_EC_ENABLE 0x02020303ul // FCH EC enabled.
-#define KERN_EVENT_EC_KBD_ENABLE 0x02010304ul // FCH IMC EC KBD enabled.
-#define KERN_EVENT_EC_CHANNEL0_ENABLE 0x02010305ul // FCH IMC EC channel0 function enabled.
-#define KERN_EVENT_IMC_INTO_SLEEP_MODE 0x02010306ul // FCH IMC goes into sleep mode.
-#define KERN_EVENT_IMC_CRASH_RESET 0x02010307ul // FCH IMC Crash Reset to prevent repeating the reset forever.
-#define KERN_EVENT_IMC_SW_DISABLE_IMC 0x02010308ul // FCH Software disable IMC thru mailbox command.
-#define KERN_EVENT_IMC_DISABLE_SUREBOOT_TIMMER 0x02010309ul // FCH Disable SureBoot Timmer.
-#define KERN_EVENT_IMC_WAKEUP 0x0201030Aul // FCH IMC wakeup command.
-#define KERN_EVENT_IMC_IDLE 0x0201030Bul // FCH IMC idle command.
-#define KERN_EVENT_EC_DISABLE 0x0201030Cul // FCH EC disable by jumper setting or board config.
-#define KERN_ERROR_IMC_FW_VALIDATE_FAILED 0x02030300ul // FCH IMC firmware validation failure.
-// PCIE/AB
-#define KERN_EVENT_AB_SLOW_SPEED_ABLINK_CLOCK 0x02010400ul // FCH Set Low Speed AB link clock.
-#define KERN_EVENT_AB_RESET_CPU_ON_SYNC_FLOOD 0x02010401ul // FCH set AB reset CPU on sync flood enabled.
-#define KERN_EVENT_AB_CLOCK_GATING_ENABLE 0x02010402ul // FCH set AB Clock Gating function enabled.
-#define KERN_EVENT_AB_CLOCK_GATING_DISABLE 0x02010403ul // FCH set AB clock Gating function disabled.
-#define KERN_EVENT_AB_DMA_MEMORY_W3264B_ENABLE 0x02010404ul // FCH set AB DMA MEMORY Write 32/64B enabled.
-#define KERN_EVENT_AB_DMA_MEMORY_W3264B_DISABLED 0x02010405ul // FCH set AB DMA MEMORY Write 32/64B disabled.
-#define KERN_EVENT_AB_MEMORY_POWERSAVING_ENABLED 0x02010406ul // FCH Set AB Memory Power Saving enabled.
-#define KERN_EVENT_AB_MEMORY_POWERSAVING_DISABLED 0x02010407ul // FCH Set AB Memory Power Saving disabled.
-#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_ENABLED 0x02010408ul // FHC set ALink clock Gate-off enabled.
-#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_DISABLED 0x02010409ul // FHC set ALink clock Gate-off disabled.
-#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_ENABLED 0x0201040Aul // FHC set BLink clock Gate-off enabled.
-#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_DISABLED 0x0201040Bul // FHC set BLink clock Gate-off disabled.
-// SATA
-#define KERN_EVENT_SATA_ENABLE 0x02010500ul // FCH set SATA controller enabled.
-#define KERN_EVENT_SATA_MAX_GEN2_MODE_ENABLE 0x02010501ul // FCH set SATA support only Max. GEN2 mode.
-#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_EXT 0x02010502ul // FCH set SATA clock source as external 48Mhz.
-#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_INT 0x02010502ul // FCH set SATA clock source as internal 48Mhz.
-#define KERN_EVENT_SATA_SET_CLK_SOURCE_100_INT 0x02010503ul // FCH set SATA clock source as internal 100Mhz.
-#define KERN_EVENT_SATA_STABLE_MEM_SHUTDOWN_ENABLE 0x02010504ul // FCH set SATA stable memory sutdown enable * Misc.
-#define KERN_EVENT_SATA_PROG_SATA_PORT_PHY 0x02010505ul // FCH programming SATA port's PHY.
-#define KERN_EVENT_SATA_READ_SQUELCH_FROM_EFUSE 0x02010506ul // FCH programming SATA squelch value from eFuse.
-#define KERN_EVENT_SATA_DISABLE 0x02010507ul // FCH set SATA controller disabled.
-#define KERN_EVENT_SATA_AHCI_MODE 0x02010508ul // FCH set SATA as AHCI mode.
-#define KERN_EVENT_SATA_IDE_2_AHCI_MODE 0x02010509ul // FCH set SATA as IDE_2_AHCI mode.
-#define KERN_EVENT_SATA_IDE_MODE 0x0201050Aul // FCH set SATA as IDE mode.
-#define KERN_EVENT_SATA_RAID_MODE 0x0201050Bul // FCH set SATA as RAID mode.
-#define KERN_EVENT_SATA_MSI_CAP_ENABLE 0x0201050Cul // FCH set SATA MSI Capability Enabled.
-#define KERN_EVENT_SATA_SUPPORT_8_DEVICE 0x0201050Dul // FCH set SATA support 8 device mode.
-#define KERN_EVENT_SATA_DISABLED_GENERIC_MODE 0x0201050Eul // FCH set SATA disable generic mode.
-#define KERN_EVENT_SATA_PHY_PLL_SHUTDOWN 0x0201050Ful // FCH set SATA PHY PLL shutdown.
-#define KERN_EVENT_SATA_OOB_DETECTION_ENH 0x02010510ul // FCH set SATA OOB Detection Enhance Mode.
-#define KERN_EVENT_SATA_MEM_POWER_SAVING 0x02010511ul // FCH set SATA memory power saving.
-#define KERN_EVENT_SATA_DEV_SLP_PORT0 0x02010512ul // FCH set SATA Deep Sleep Mode on Port0.
-#define KERN_EVENT_SATA_DEV_SLP_PORT1 0x02010513ul // FCH set SATA Deep Sleep Mode on Port1.
-#define KERN_EVENT_SATA_AHCI_DIS_PREFETCH 0x02010514ul // FCH set SATA AHCI disable Prefetch.
-#define KERN_EVENT_SATA_PORT_MULT_CAP 0x02010515ul // FCH set SATA Port Mult Capability Enabled.
-#define KERN_EVENT_SATA_FIS_BASE_SWITCHING 0x02010516ul // FCH set SATA support FIS-based switching.
-#define KERN_EVENT_SATA_AGGR_LINK_PM_CAP 0x02010517ul // FCH set SATA aggressive link power management.
-#define KERN_EVENT_SATA_PSC_CAP 0x02010518ul // FCH set SATA support partial state.
-#define KERN_EVENT_SATA_SSC_CAP 0x02010519ul // FCH set SATA support Slumber mode.
-#define KERN_EVENT_SATA_CCC_CAP 0x0201051Aul // FCH set SATA support command completion coalescing.
-#define KERN_EVENT_SATA_AHCI_ENCLOSURE_MANAGEMENT 0x0201051Bul // FCH set SATA support Enclosure Management.
-#define KERN_EVENT_SATA_ESP_PORT_ENABLE 0x0201051Cul // FCH set SATA ESP ports (one of ESP ports are set).
-#define KERN_EVENT_SATA_BIOS_OS_HANDOFF 0x0201051Dul // FCH set SATA HBA supports the BIOS/OS handoff mechanism.
-#define KERN_EVENT_SATA_DRIVE_DETECTION 0x0201051Eul // FCH SATA is excuting SATA drive detection.
-#define KERN_EVENT_SATA_CLK_AUTO_OFF 0x0201051Ful // FCH set SATA Auto Clock off function.
-#define KERN_EVENT_SATA_PORT_GEN_MODE 0x02010520ul // FCH set SATA port GEN mode.
-#define KERN_EVENT_SATA_HOT_REMOVAL_ENH 0x02010521ul // FCH set SATA hot removal enhance mode.
-// SD
-#define KERN_EVENT_SD_ENABLE 0x02010600ul // FCH set SD controller to enable.
-#define KERN_EVENT_SD_AS_DMA_MODE 0x02010601ul // FCH set SD as DMA mode.
-#define KERN_EVENT_SD_AS_PIO_MODE 0x02010602ul // FCH set SD as PIO mode.
-#define KERN_EVENT_SD_AS_2_0_MODE 0x02010603ul // FCH set SD as 2.0 mode.
-#define KERN_EVENT_SD_AS_3_0_MODE 0x02010604ul // FCH set SD as 3.0 mode.
-#define KERN_EVENT_SD_CLOCK_MULTIPLIER 0x02010605ul // FCH set SD clock multiplier.
-#define KERN_EVENT_SD_DISABLE 0x02010606ul // FCH set SD controller to disable.
-// LPC/SPI
-#define KERN_EVENT_LPC_CLK0_DISABLE 0x02010700ul // FCH set LPC0 clock disabled.
-#define KERN_EVENT_LPC_CLK1_DISABLE 0x02010701ul // FCH set LPC1 clock disabled.
-#define KERN_EVENT_LPC_LEGACY_FREE_MODE 0x02010702ul // FCH set LPC as legacy free mode.
-#define KERN_EVENT_SPI_QUAL_MODE 0x02010703ul // FCH SPI Qual Mode is enabled (by user selection).
-#define KERN_EVENT_SPI_SPEED 0x02010704ul // FCH SPI speed is set by user selection.
-#define KERN_EVENT_SPI_FAST_SPEED 0x02010705ul // FCH SPI fast speed is set.
-#define KERN_EVENT_SPI_QUALIFY_QUAL_MODE 0x02010706ul // FCH SPI Qual Mode is validated.
-// USB
-#define KERN_ERROR_USB_ROMSIG_NOT_FOUND 0x02030800ul // FCH ROMSIG not found.
-#define KERN_ERROR_USB_XHCI_FW_FOUND 0x02030801ul // FCH XHCI firmware does not exist.
-#define KERN_EVENT_USB_EHCI1_ENABLE 0x02010800ul // FCH set EHCI1 enable.
-#define KERN_EVENT_USB_EHCI2_ENABLE 0x02010801ul // FCH set EHCI2 enable.
-#define KERN_EVENT_USB_EHCI3_ENABLE 0x02010802ul // FCH set EHCI3 enable.
-#define KERN_EVENT_USB_XHCI_DISABLE 0x02010803ul // FCH set XHCI disable.
-#define KERN_EVENT_USB_PHY_POWER_DOWN 0x02010804ul // FCH set USB PHY powerdown enable.
-#define KERN_EVENT_USB_PHY_CALIBRATED 0x02010805ul // FCH set USB PHY calibrated.
-#define KERN_EVENT_USB_PORT_PHY_SETTING 0x02010806ul // FCH set USB Port PHY setting.
-#define KERN_EVENT_USB_PORT_PHY_CLK_GATING 0x02010807ul // FCH set USB Port PHY Clock Gating.
-#define KERN_EVENT_USB_XHCI_USED_PREDEFINE_ADDRESS 0x02010808ul // FCH XHCI ROM location is used user-define address.
-#define KERN_EVENT_USB_XHCI_BOOTRAM_PRELOAD 0x02010809ul // FCH XHCI preload its BOOTRAM.
-#define KERN_EVENT_USB_XHCI_INSTRUCTRAM_PRELOAD 0x0201080Aul // FCH XHCI preload its InstructionRAM.
-#define KERN_EVENT_USB_XHCI_ROM_PREINIT_COMPLETED 0x0201080Bul // FCH XHCI preinit completed.
-#define KERN_EVENT_USB_XHCI0_ENABLE 0x0201080Cul // FCH set XHCI0 enable.
-#define KERN_EVENT_USB_XHCI1_ENABLE 0x0201080Dul // FCH set XHCI1 enable.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 01:19:44 +0000