diff options
| author | David Hendricks <dhendrix@chromium.org> | 2015-02-02 17:17:29 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:58:40 +0200 |
| commit | 44004b370860146409f4b099c0a1f26afafefffe (patch) | |
| tree | 53058316db5c9e142af8b74b3e2261812bc5eeff | |
| parent | e18c38e3ba2fdccee94531c72441b6aa87f2044c (diff) | |
| download | coreboot-44004b370860146409f4b099c0a1f26afafefffe.tar.xz | |
veyron_{brain,danger,rialto}: Use common watchdog reboot
This applies a previous patch ("chromeos: Provide common watchdog
reboot support") to some veyron platforms that were missing it.
BUG=none
BRANCH=none
TEST=built and booted on Brain
Change-Id: I3eb431a57367b8f885844e4353a78f77515f5195
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b0c87dd4217917a35817c719efe43dd4ec442df0
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I2861939655a995d309847f64cecd974a740fae37
Original-Reviewed-on: https://chromium-review.googlesource.com/245633
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/9754
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
| -rw-r--r-- | src/mainboard/google/veyron_brain/bootblock.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_danger/bootblock.c | 8 | ||||
| -rw-r--r-- | src/mainboard/google/veyron_rialto/bootblock.c | 8 |
3 files changed, 9 insertions, 15 deletions
diff --git a/src/mainboard/google/veyron_brain/bootblock.c b/src/mainboard/google/veyron_brain/bootblock.c index 610c23e4de..8650e0eea2 100644 --- a/src/mainboard/google/veyron_brain/bootblock.c +++ b/src/mainboard/google/veyron_brain/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + gpio_output(GPIO(7, A, 0), 1); /* Power LED */ /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ @@ -60,11 +63,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) { - printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n"); - hard_reset(); - } - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_danger/bootblock.c b/src/mainboard/google/veyron_danger/bootblock.c index 610c23e4de..8650e0eea2 100644 --- a/src/mainboard/google/veyron_danger/bootblock.c +++ b/src/mainboard/google/veyron_danger/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + gpio_output(GPIO(7, A, 0), 1); /* Power LED */ /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ @@ -60,11 +63,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) { - printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n"); - hard_reset(); - } - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); diff --git a/src/mainboard/google/veyron_rialto/bootblock.c b/src/mainboard/google/veyron_rialto/bootblock.c index a1a2ba73b8..86104ece38 100644 --- a/src/mainboard/google/veyron_rialto/bootblock.c +++ b/src/mainboard/google/veyron_rialto/bootblock.c @@ -45,6 +45,9 @@ void bootblock_mainboard_early_init() void bootblock_mainboard_init(void) { + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + /* Up VDD_CPU (BUCK1) to 1.4V to support max CPU frequency (1.8GHz). */ setbits_le32(&rk3288_pmu->iomux_i2c0scl, IOMUX_I2C0SCL); setbits_le32(&rk3288_pmu->iomux_i2c0sda, IOMUX_I2C0SDA); @@ -58,11 +61,6 @@ void bootblock_mainboard_init(void) udelay(100);/* Must wait for voltage to stabilize,2mV/us */ rkclk_configure_cpu(); - if (rkclk_was_watchdog_reset()) { - printk(BIOS_INFO, "Last reset was watchdog... rebooting via GPIO!\n"); - hard_reset(); - } - /* i2c1 for tpm */ writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1); i2c_init(1, 400*KHz); |