diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2017-02-23 13:14:44 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-02 22:14:53 +0100 |
| commit | 44a3066015ec4576ce5b71be5b3fe06e41680fc9 (patch) | |
| tree | 213c9684137e5b228edf129ae0c846739699f96a | |
| parent | b2bb6ad2a72a926796a7eaede06ef8acd556c472 (diff) | |
| download | coreboot-44a3066015ec4576ce5b71be5b3fe06e41680fc9.tar.xz | |
nb/i945: Clean "Programming DLL Timings" function
As we drive both channels with the same speed,
chan0dll and chan1dll are the same.
Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18472
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
| -rw-r--r-- | src/northbridge/intel/i945/raminit.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7ccefbd92..b5cce9c429 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1227,7 +1227,7 @@ static void sdram_enable_rcomp(void) static void sdram_program_dll_timings(struct sys_info *sysinfo) { - u32 chan0dll = 0, chan1dll = 0; + u32 channeldll = 0; int i; printk(BIOS_DEBUG, "Programming DLL Timings...\n"); @@ -1238,26 +1238,26 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo) /* We drive both channels with the same speed */ if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x26262626; chan1dll = 0x26262626; break; /* 400MHz */ - case 533: chan0dll = 0x22222222; chan1dll = 0x22222222; break; /* 533MHz */ - case 667: chan0dll = 0x11111111; chan1dll = 0x11111111; break; /* 667MHz */ + case 400: channeldll = 0x26262626; break; + case 533: channeldll = 0x22222222; break; + case 667: channeldll = 0x11111111; break; } } else if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { switch (sysinfo->memory_frequency) { - case 400: chan0dll = 0x33333333; chan1dll = 0x33333333; break; /* 400MHz */ - case 533: chan0dll = 0x24242424; chan1dll = 0x24242424; break; /* 533MHz */ - case 667: chan0dll = 0x25252525; chan1dll = 0x25252525; break; /* 667MHz */ + case 400: channeldll = 0x33333333; break; + case 533: channeldll = 0x24242424; break; + case 667: channeldll = 0x25252525; break; } } for (i = 0; i < 4; i++) { - MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = chan0dll; - MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = chan0dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = chan1dll; - MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = chan1dll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C0R0B00DQST + (i * 0x10) + 4) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 0) = channeldll; + MCHBAR32(C1R0B00DQST + (i * 0x10) + 4) = channeldll; if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC)) { - MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = chan0dll & 0xff; - MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = chan1dll & 0xff; + MCHBAR8(C0R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; + MCHBAR8(C1R0B00DQST + (i * 0x10) + 8) = channeldll & 0xff; } } } |