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authorRonald G. Minnich <rminnich@gmail.com>2003-07-23 01:41:55 +0000
committerRonald G. Minnich <rminnich@gmail.com>2003-07-23 01:41:55 +0000
commit4dc7b80151952385c217e924648de151185e24a0 (patch)
tree198d9e708b90c1d00a681e363329e28bc40d04ad
parentfd0adfe86c670c8099c791354a9f7d5526dcf356 (diff)
downloadcoreboot-4dc7b80151952385c217e924648de151185e24a0.tar.xz
updated for new code.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1003 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/arima/hdama/Config.lb50
1 files changed, 32 insertions, 18 deletions
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
index 77e68701d8..a09329dd73 100644
--- a/src/mainboard/arima/hdama/Config.lb
+++ b/src/mainboard/arima/hdama/Config.lb
@@ -47,12 +47,6 @@ end
#
#### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
-###
-### Setup the serial port
-###
-#mainboardinit superiowinbond/w83627hf/setup_serial.inc
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
#
###
### Include an id string (For safe flashing)
@@ -74,16 +68,24 @@ end
### Setup our mtrrs
###
mainboardinit cpu/k8/earlymtrr.inc
-#
-#
###
### Only the bootstrap cpu makes it here.
### Failover if we need to
###
#
if USE_FALLBACK_IMAGE
- mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
+ mainboardinit ./failover.inc
+# mainboardinit southbridge/amd/amd8111/cmos_boot_failover.inc
end
+
+#
+#
+###
+### Setup the serial port
+###
+#mainboardinit superiowinbond/w83627hf/setup_serial.inc
+mainboardinit pc80/serial.inc
+mainboardinit arch/i386/lib/console.inc
#
####
#### O.k. We aren't just an intermediary anymore!
@@ -99,7 +101,7 @@ end
# mainboardinit southbridgeamd/amd8111/disable_watchdog.inc
#end
#
-if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
+#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#
###
### Romcc output
@@ -107,22 +109,34 @@ if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc end
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
#mainboardinit .failover.inc
+
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
+end
+
+makerule ./failover.inc
+ depends "./romcc ./failover.E"
+ action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
+
makerule ./auto.E
depends "$(MAINBOARD)/auto.c"
- action "$(CPP) -I$(TOP)/src -$(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+ action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
end
makerule ./auto.inc
depends "./romcc ./auto.E"
- action "./romcc -O ./auto.E > auto.inc"
+ action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
end
+mainboardinit cpu/k8/enable_mmx_sse.inc
mainboardinit ./auto.inc
+mainboardinit cpu/k8/disable_mmx_sse.inc
#
###
### Setup RAM
###
-mainboardinit ram/ramtest.inc
-mainboardinit southbridge/amd/amd8111/smbus.inc
-mainboardinit sdram/generic_dump_spd.inc
+#mainboardinit ram/ramtest.inc
+#mainboardinit southbridge/amd/amd8111/smbus.inc
+#mainboardinit sdram/generic_dump_spd.inc
#
###
### Include the secondary Configuration files
@@ -131,9 +145,11 @@ northbridge amd/amdk8
end
southbridge amd/amd8111
end
+southbridge amd/amd8131
+end
#mainboardinit archi386/smp/secondary.inc
superio NSC/pc87360
- register ".com1={1}, .com2={0}, .floppy=1, .lpt=1, .keyboard=1"
+ register ".com1={1}, .lpt=1"
end
dir /pc80
##dir /src/superio/winbond/w83627hf
@@ -141,5 +157,3 @@ cpu p5 end
cpu p6 end
cpu k7 end
cpu k8 end
-
-makedefine CFLAGS += -g