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authorMartin Roth <martinroth@google.com>2015-11-18 16:36:40 -0700
committerMartin Roth <martinroth@google.com>2015-11-20 16:36:08 +0100
commit5cf5828c02f1a10421417c63a5cd26bfa125a932 (patch)
tree5a87e981f6c22b6b68c909437a84a8ebaaaa958f
parentd2e8f6ad33c750853844c5674d1a1a926ad7d93a (diff)
downloadcoreboot-5cf5828c02f1a10421417c63a5cd26bfa125a932.tar.xz
fsp1_0: Remove hardcoded microcode locations
These are no longer needed. Test: Booted minnowmax. Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/12468 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
-rw-r--r--src/cpu/intel/fsp_model_406dx/Kconfig5
-rw-r--r--src/soc/intel/fsp_baytrail/Kconfig4
2 files changed, 0 insertions, 9 deletions
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig
index 30e7e592bc..c36851d485 100644
--- a/src/cpu/intel/fsp_model_406dx/Kconfig
+++ b/src/cpu/intel/fsp_model_406dx/Kconfig
@@ -53,11 +53,6 @@ config ENABLE_VMX
bool "Enable VMX for virtualization"
default n
-config CPU_MICROCODE_CBFS_LOC
- hex
- depends on SUPPORT_CPU_UCODE_IN_CBFS
- default 0xfff60040
-
config HAVE_CPU_MICROCODE_FILE
bool "Add microcode file"
help
diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index ff233083d4..2325d75838 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -86,10 +86,6 @@ config VGA_BIOS_ID
This is the default PCI ID for the Bay Trail graphics
devices. This string names the vbios ROM in cbfs.
-config CPU_MICROCODE_CBFS_LOC
- hex
- default 0xfff10040
-
config ENABLE_BUILTIN_COM1
bool "Enable built-in legacy Serial Port"
help