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authorElyes HAOUAS <ehaouas@noos.fr>2017-12-20 21:25:12 +0100
committerPatrick Georgi <pgeorgi@google.com>2018-06-14 10:00:03 +0000
commit5e2ac2c0795628ab086da76304cd97b16e1d169f (patch)
tree515b6e2346ab0bd03fa4916ad165a0521ff7c0a1
parente73a85c5a51cb6e39ecaaca3ba497a81c86ee398 (diff)
downloadcoreboot-5e2ac2c0795628ab086da76304cd97b16e1d169f.tar.xz
nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce
Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/22957 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/include/cpu/x86/tsc.h2
-rw-r--r--src/northbridge/intel/fsp_rangeley/udelay.c2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 4cf4fbc5b0..35c8a820d5 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -11,6 +11,8 @@
#define TSC_SYNC
#endif
+#define MSR_PLATFORM_INFO 0xce
+
struct tsc_struct {
unsigned int lo;
unsigned int hi;
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index 5aca22974f..01989abb37 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -43,7 +43,7 @@ void udelay(u32 us)
u32 fsb = 100, divisor;
u32 d; /* ticks per us */
- msr = rdmsr(0xce);
+ msr = rdmsr(MSR_PLATFORM_INFO);
divisor = (msr.lo >> 8) & 0xff;
d = fsb * divisor;