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authorDuncan Laurie <dlaurie@google.com>2018-12-10 11:29:36 -0800
committerDuncan Laurie <dlaurie@chromium.org>2018-12-14 18:30:24 +0000
commit6217e9beff16d805ca833e79a2931bcdb3d02a44 (patch)
tree44e02799c5515561ef3108286b26c140a49f7b32
parent28e8ae5385668bb7c26666c0a0bf0208231da78f (diff)
downloadcoreboot-6217e9beff16d805ca833e79a2931bcdb3d02a44.tar.xz
vendorcode/google/chromeos: Get ACPI pin from GPIO library
If the generic GPIO library is enabled the code that generates the GPIO table in ACPI should attempt to get the GPIO pin value from the gpio_acpi_pin() function. BUG=b:120686247 TEST=Tested on Sarien board to ensure that GPIO pin exported by Chrome OS for the Write Protect signal is correct. Change-Id: I267694b576009f79bacac6eda5f32bbf51742d78 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/30132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r--src/vendorcode/google/chromeos/acpi.c10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c
index 6605809023..13c757633b 100644
--- a/src/vendorcode/google/chromeos/acpi.c
+++ b/src/vendorcode/google/chromeos/acpi.c
@@ -14,6 +14,9 @@
*/
#include <arch/acpigen.h>
+#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+#include <gpio.h>
+#endif
#include "chromeos.h"
void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num)
@@ -28,7 +31,12 @@ void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num)
acpigen_write_package(4);
acpigen_write_integer(gpios[i].type);
acpigen_write_integer(gpios[i].polarity);
- acpigen_write_integer(gpios[i].gpio_num);
+ /* Get ACPI pin from GPIO library if available */
+#if IS_ENABLED(CONFIG_GENERIC_GPIO_LIB)
+ acpigen_write_integer(gpio_acpi_pin(gpios[i].gpio_num));
+#else
+ acpigen_write_integer(gpios[i].gpio_num);
+#endif
acpigen_write_string(gpios[i].device);
acpigen_pop_len();
}