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authorNico Huber <nico.h@gmx.de>2018-11-21 00:11:35 +0100
committerPatrick Georgi <pgeorgi@google.com>2019-02-18 20:24:50 +0000
commit6275e345234383a249c8a44a777e1937219628fa (patch)
tree5f4fc61d984ab4ac6b0fd420ffd6e1f09b5cfe73
parentcd7873a28a311847bdd1fd7f74d2a6d0f66ede62 (diff)
downloadcoreboot-6275e345234383a249c8a44a777e1937219628fa.tar.xz
soc/intel/skylake: Use real common code for VMX init
Use the common VMX implementation, and set IA32_FEATURE_CONTROL lock bit per Kconfig *after* SGX is configured (as SGX also sets bits on the IA32_FEATURE_CONTROL register). As it is now correctly based on a Kconfig, the `VmxEnable` devicetree setting vanishes. Test: build/boot google/[chell,fizz], observe Virtualization enabled under Windows 10 when VMX enabled and lock bit set. Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/29682 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/eve/devicetree.cb1
-rw-r--r--src/mainboard/google/fizz/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/variants/asuka/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/variants/caroline/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/variants/cave/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/variants/chell/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/variants/glados/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/variants/lars/devicetree.cb1
-rw-r--r--src/mainboard/google/glados/variants/sentry/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/atlas/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/baseboard/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nami/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nautilus/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/nocturne/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/rammus/devicetree.cb1
-rw-r--r--src/mainboard/google/poppy/variants/soraka/devicetree.cb1
-rw-r--r--src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb3
-rw-r--r--src/mainboard/intel/kunimitsu/devicetree.cb3
-rw-r--r--src/mainboard/intel/saddlebrook/devicetree.cb2
-rw-r--r--src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb1
-rw-r--r--src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb1
-rw-r--r--src/soc/intel/skylake/Kconfig2
-rw-r--r--src/soc/intel/skylake/chip.h3
-rw-r--r--src/soc/intel/skylake/chip_fsp20.c2
-rw-r--r--src/soc/intel/skylake/cpu.c33
-rw-r--r--src/soc/intel/skylake/romstage/romstage_fsp20.c2
26 files changed, 16 insertions, 52 deletions
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 44449a5d2e..66c1c53e2c 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -52,7 +52,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index c7c35c04d2..07a453d73d 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -88,7 +88,6 @@ chip soc/intel/skylake
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
register "SendVrMbxCmd" = "1" # IMVP8 workaround
- register "VmxEnable" = "1"
# Intersil VR c-state issue workaround
# send VR mailbox command for IA/GT/SA rails
diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb
index b9e87a873b..d365e8fd34 100644
--- a/src/mainboard/google/glados/variants/asuka/devicetree.cb
+++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 4s
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb
index 8caf8fde2e..cffb6df0e3 100644
--- a/src/mainboard/google/glados/variants/caroline/devicetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb
@@ -54,7 +54,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
# TCC offset
register "tcc_offset" = "10"
diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb
index f512f9bc87..e0c7fc7ed6 100644
--- a/src/mainboard/google/glados/variants/cave/devicetree.cb
+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb
@@ -54,7 +54,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb
index 3343aa0103..1b87cca93e 100644
--- a/src/mainboard/google/glados/variants/chell/devicetree.cb
+++ b/src/mainboard/google/glados/variants/chell/devicetree.cb
@@ -54,7 +54,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb
index 2472dde515..f4e09a6b7d 100644
--- a/src/mainboard/google/glados/variants/glados/devicetree.cb
+++ b/src/mainboard/google/glados/variants/glados/devicetree.cb
@@ -54,7 +54,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb
index d552010d0e..56087ad1f0 100644
--- a/src/mainboard/google/glados/variants/lars/devicetree.cb
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -42,7 +42,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 4s
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb
index 7a891949f5..0effbd73c8 100644
--- a/src/mainboard/google/glados/variants/sentry/devicetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb
@@ -44,7 +44,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "3" # 4s
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index 275b27d065..adf51b7877 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -60,7 +60,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "speed_shift_enable" = "1"
register "tdp_pl2_override" = "15"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index ad1e628bdd..251cab8a88 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -57,7 +57,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index d4e5d2f825..5d9c096c05 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -56,7 +56,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
# Intersil VR c-state issue workaround
# send VR mailbox command for IA/GT/SA rails
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 37edd8af91..75a01c2541 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -57,7 +57,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 76b97732d8..4d9403c92b 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -62,7 +62,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
# Set speed_shift_enable to 1 to enable P-States, and 0 to disable
register "speed_shift_enable" = "1"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index cf3259347d..c8e4008fd1 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -60,7 +60,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index ddf74a15f3..4713a816ac 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -57,7 +57,6 @@ chip soc/intel/skylake
register "PmConfigSlpSusMinAssert" = "1" # 500ms
register "PmConfigSlpAMinAssert" = "3" # 2s
register "PmTimerDisabled" = "1"
- register "VmxEnable" = "1"
register "pirqa_routing" = "PCH_IRQ11"
register "pirqb_routing" = "PCH_IRQ10"
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index be9d1dffe8..51399dc80f 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -126,9 +126,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
- # Enable/Disable VMX feature
- register "VmxEnable" = "0"
-
device cpu_cluster 0 on
device lapic 0 on end
end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index ffa259b7f6..4b720bf88b 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -186,9 +186,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
- # Enable/Disable VMX feature
- register "VmxEnable" = "0"
-
# Use default SD card detect GPIO configuration
register "sdcard_cd_gpio_default" = "GPP_A7"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index e541bfe5af..7036b28f2d 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -247,8 +247,6 @@ chip soc/intel/skylake
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
- # Enable/Disable VMX feature
- register "VmxEnable" = "0"
# Use default SD card detect GPIO configuration
#register "sdcard_cd_gpio_default" = "GPP_A7"
diff --git a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
index a4fd502dbe..399c6432a1 100644
--- a/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem13v2/devicetree.cb
@@ -8,7 +8,6 @@ chip soc/intel/skylake
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
register "eist_enable" = "1"
- register "VmxEnable" = "1"
# Set the Thermal Control Circuit (TCC) activaction value to 95C
# even though FSP integration guide says to set it to 100C for SKL-U
diff --git a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
index 7ff3dad399..f9f7ef7e53 100644
--- a/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/variants/librem15v3/devicetree.cb
@@ -8,7 +8,6 @@ chip soc/intel/skylake
register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
register "eist_enable" = "1"
- register "VmxEnable" = "1"
# Set the Thermal Control Circuit (TCC) activaction value to 95C
# even though FSP integration guide says to set it to 100C for SKL-U
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 506a04165b..77d259b21b 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select COLLECT_TIMESTAMPS
select COMMON_FADT
+ select CPU_INTEL_COMMON
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select C_ENVIRONMENT_BOOTBLOCK
select FSP_M_XIP if MAINBOARD_USES_FSP2_0
@@ -65,7 +66,6 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_UART
- select SOC_INTEL_COMMON_BLOCK_VMX
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index 39e5056bca..f131a1a5df 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -465,9 +465,6 @@ struct soc_intel_skylake_config {
*/
u8 SendVrMbxCmd;
- /* Enable/Disable VMX feature */
- u8 VmxEnable;
-
/*
* PRMRR size setting with three options
* 0x02000000 - 32MiB
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 3ade8d72cf..f4e17c640b 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -322,7 +322,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->LogoPtr = config->LogoPtr;
params->LogoSize = config->LogoSize;
- params->CpuConfig.Bits.VmxEnable = config->VmxEnable;
+ params->CpuConfig.Bits.VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX);
params->PchPmWoWlanEnable = config->PchPmWoWlanEnable;
params->PchPmWoWlanDeepSxEnable = config->PchPmWoWlanDeepSxEnable;
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index 413fbbb130..910dcb88c9 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -27,6 +27,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/mp.h>
+#include <cpu/intel/common/common.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
@@ -39,7 +40,6 @@
#include <intelblocks/mp_init.h>
#include <intelblocks/sgx.h>
#include <intelblocks/smm.h>
-#include <intelblocks/vmx.h>
#include <soc/cpu.h>
#include <soc/msr.h>
#include <soc/pci_devs.h>
@@ -467,6 +467,16 @@ static void per_cpu_smm_trigger(void)
smm_relocate();
}
+static void vmx_configure(void *unused)
+{
+ set_feature_ctrl_vmx();
+}
+
+static void fc_lock_configure(void *unused)
+{
+ set_feature_ctrl_lock();
+}
+
static void post_mp_init(void)
{
/* Set Max Ratio */
@@ -486,6 +496,8 @@ static void post_mp_init(void)
mp_run_on_all_cpus(vmx_configure, NULL, 2 * USECS_PER_MSEC);
mp_run_on_all_cpus(sgx_configure, NULL, 14 * USECS_PER_MSEC);
+
+ mp_run_on_all_cpus(fc_lock_configure, NULL, 2 * USECS_PER_MSEC);
}
static const struct mp_ops mp_ops = {
@@ -566,22 +578,3 @@ int soc_fill_sgx_param(struct sgx_param *sgx_param)
sgx_param->enable = conf->sgx_enable;
return 0;
}
-int soc_fill_vmx_param(struct vmx_param *vmx_param)
-{
- struct device *dev = SA_DEV_ROOT;
- config_t *conf;
-
- if (!dev) {
- printk(BIOS_ERR, "Failed to get root dev for checking VMX param\n");
- return -1;
- }
-
- conf = dev->chip_info;
- if (!conf) {
- printk(BIOS_ERR, "Failed to get chip_info for VMX param\n");
- return -1;
- }
-
- vmx_param->enable = conf->VmxEnable;
- return 0;
-}
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 2a601588d6..6fe79f66f6 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -225,7 +225,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->RMT = config->Rmt;
m_cfg->CmdTriStateDis = config->CmdTriStateDis;
m_cfg->DdrFreqLimit = config->DdrFreqLimit;
- m_cfg->VmxEnable = config->VmxEnable;
+ m_cfg->VmxEnable = IS_ENABLED(CONFIG_ENABLE_VMX);
m_cfg->PrmrrSize = config->PrmrrSize;
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
if (config->PcieRpEnable[i])