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| author | Patrick Rudolph <siro@das-labor.org> | 2017-10-31 11:36:55 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-07-26 14:11:38 +0000 |
| commit | 652c491917dce44be6fe0bdce475824af3d43c87 (patch) | |
| tree | b680131d04445d73a70282fe2a7e95d7ca904705 | |
| parent | 8ba9e8cf63f92902cdb71eb5c4d3b3ea579380f4 (diff) | |
| download | coreboot-652c491917dce44be6fe0bdce475824af3d43c87.tar.xz | |
nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops
On desktop boards the PPD bit of MRS register MR0 is set and thus
DLL_Off mode shouldn't be used, as enforced by datasheet
2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.17.1.
Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 9 | ||||
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.h | 5 |
2 files changed, 11 insertions, 3 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3e769ec5a4..44f7f6d82c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3202,7 +3202,14 @@ void final_registers(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK - write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740); + + if (ctrl->mobile) + /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ + MCHBAR32(PM_PDWN_Config) = 0x00000740; + else + /* APD - PPD, 64 DCLKs until idle, decision per rank */ + MCHBAR32(PM_PDWN_Config) = 0x00000340; + write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 1f32dcddc4..28849e737a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -150,8 +150,9 @@ typedef struct ramctr_timing_st { #define MAKE_ERR ((channel<<16)|(slotrank<<8)|1) #define GET_ERR_CHANNEL(x) (x>>16) -#define MC_BIOS_REQ 0x5e00 -#define MC_BIOS_DATA 0x5e04 +#define MC_BIOS_REQ 0x5e00 +#define MC_BIOS_DATA 0x5e04 +#define PM_PDWN_Config 0x4cb0 u8 get_CWL(u32 tCK); void dram_mrscommands(ramctr_timing * ctrl); |