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authorHuayang Duan <huayang.duan@mediatek.com>2020-01-20 11:42:42 +0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-25 10:20:55 +0000
commit68bb307418a691359bddb801a7b7a2c48c5c1297 (patch)
treeafb841778ce84ff83f879bbc3f17a60d8adad54b
parentd2bba86bf7200362d8801fa475bc2c1ff935c8d7 (diff)
downloadcoreboot-68bb307418a691359bddb801a7b7a2c48c5c1297.tar.xz
soc/mediatek/mt8183: Fix programming error of DRAMC setting
1. The ac timing of 2400Mbps should use diff params with 1600Mbps. 2. Fix the typo error of save shuffle function for DVFS. BRANCH=kukui BUG=none TEST=emerge-kukui coreboot Change-Id: I5edac32938def50836f386426e7deb652b80d42d Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
-rw-r--r--src/soc/mediatek/mt8183/emi.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c
index cf104f8485..07d1cc8ee5 100644
--- a/src/soc/mediatek/mt8183/emi.c
+++ b/src/soc/mediatek/mt8183/emi.c
@@ -325,7 +325,7 @@ static void dramc_ac_timing_optimize(u8 freq_group)
{
struct optimize_ac_time rf_cab_opt[LP4X_DDRFREQ_MAX] = {
[LP4X_DDR1600] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62},
- [LP4X_DDR2400] = {.rfc = 44, .rfc_05t = 0, .tx_ref_cnt = 62},
+ [LP4X_DDR2400] = {.rfc = 72, .rfc_05t = 0, .tx_ref_cnt = 91},
[LP4X_DDR3200] = {.rfc = 100, .rfc_05t = 0, .tx_ref_cnt = 119},
[LP4X_DDR3600] = {.rfc = 118, .rfc_05t = 1, .tx_ref_cnt = 138},
};
@@ -456,9 +456,9 @@ static void dramc_save_result_to_shuffle(u32 src_shuffle, u32 dst_shuffle)
value = read32(src_addr) & 0x7f;
if (dst_shuffle == DRAM_DFS_SHUFFLE_2)
- clrsetbits32(dst_addr, 0x7f << 0x8, value << 0x8);
+ clrsetbits32(dst_addr, 0x7f << 8, value << 8);
else if (dst_shuffle == DRAM_DFS_SHUFFLE_3)
- clrsetbits32(dst_addr, 0x7f << 0x16, value << 0x16);
+ clrsetbits32(dst_addr, 0x7f << 16, value << 16);
/* DRAMC-exception-2 */
src_addr = (u8 *)&ch[chn].ao.dvfsdll;