summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAaron Durbin <adurbin@chromium.org>2013-10-21 12:11:17 -0500
committerAaron Durbin <adurbin@google.com>2014-02-16 20:38:40 +0100
commit70400284b94e1a4f21be0b97df361af71f363870 (patch)
tree997ce483edcd6d39b24bb7fe14423aab48166e47
parent9956b72d567268dec936238f8da5e3e8451bfb8c (diff)
downloadcoreboot-70400284b94e1a4f21be0b97df361af71f363870.tar.xz
rambi: add BSP lapic device
There's some baked in assumptions internal to coreboot that the BSP's cpu device exists in the device tree. Therefore provide one in the device tree. BUG=chrome-os-partner:22862 BRANCH=None TEST=Compiled and booted with other changes. Change-Id: I22ba10964760ee8efbc5bbd5d4ce65daf31b3839 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/173702 Reviewed-on: http://review.coreboot.org/4887 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
-rw-r--r--src/mainboard/google/rambi/devicetree.cb4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb
index 376aab6562..c6ea97cb76 100644
--- a/src/mainboard/google/rambi/devicetree.cb
+++ b/src/mainboard/google/rambi/devicetree.cb
@@ -1,5 +1,7 @@
chip soc/intel/baytrail
- device cpu_cluster 0 on end
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
device domain 0 on
device pci 00.0 on end # SoC router
device pci 02.0 on end # GFX