diff options
| author | Ed Swierk <eswierk@arastra.com> | 2008-03-30 11:31:15 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-03-30 11:31:15 +0000 |
| commit | 71f846c13769f037fbdf649224d03377948b7fa9 (patch) | |
| tree | 8fb04b3d55db914af98a7f35e89f6b5af1799679 | |
| parent | 1e185e8561bc42b0f77159e4fa7ef0c652a2f6eb (diff) | |
| download | coreboot-71f846c13769f037fbdf649224d03377948b7fa9.tar.xz | |
Like other Intel chipsets, the Intel 3100 has a TCO timer that reboots
the system automatically unless software resets the timer
periodically. The extra reboot extends boot time by several seconds.
The attached patch adds a function to the Intel 3100 southbridge code
that halts the TCO timer, thus preventing this extra reboot, and calls
the function early in the boot process on the Mt. Arvon board.
It also fixes a bug in the LPC device initialization -- the ACPI BAR
enable flag is bit 7, not bit 4.
Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3198 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/mainboard/intel/mtarvon/auto.c | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_early_lpc.c | 20 | ||||
| -rw-r--r-- | src/southbridge/intel/i3100/i3100_lpc.c | 2 |
3 files changed, 24 insertions, 1 deletions
diff --git a/src/mainboard/intel/mtarvon/auto.c b/src/mainboard/intel/mtarvon/auto.c index 643e9841ec..dd4b76346c 100644 --- a/src/mainboard/intel/mtarvon/auto.c +++ b/src/mainboard/intel/mtarvon/auto.c @@ -90,6 +90,9 @@ static void main(unsigned long bist) uart_init(); console_init(); + /* Prevent the TCO timer from rebooting us */ + i3100_halt_tco_timer(); + /* Halt if there was a built in self test failure */ report_bist_failure(bist); diff --git a/src/southbridge/intel/i3100/i3100_early_lpc.c b/src/southbridge/intel/i3100/i3100_early_lpc.c index 2fdb3dfa09..fbefcd6acb 100644 --- a/src/southbridge/intel/i3100/i3100_early_lpc.c +++ b/src/southbridge/intel/i3100/i3100_early_lpc.c @@ -30,3 +30,23 @@ static void i3100_enable_superio(void) /* Enable decoding of I/O locations for SuperIO devices */ pci_write_config16(dev, 0x82, 0x340f); } + +static void i3100_halt_tco_timer(void) +{ + device_t dev; + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_3100_LPC), 0); + if (dev == PCI_DEV_INVALID) { + die("LPC bridge not found\r\n"); + } + + /* Temporarily enable the ACPI I/O range at 0x4000 */ + pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); + pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); + + /* Halt the TCO timer, preventing SMI and automatic reboot */ + outw(inw(0x4068) | (1 << 11), 0x4068); + + /* Disable the ACPI I/O range */ + pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7)); +} diff --git a/src/southbridge/intel/i3100/i3100_lpc.c b/src/southbridge/intel/i3100/i3100_lpc.c index 8914ed73de..b4fd5ca6d2 100644 --- a/src/southbridge/intel/i3100/i3100_lpc.c +++ b/src/southbridge/intel/i3100/i3100_lpc.c @@ -276,7 +276,7 @@ static void i3100_lpc_enable_resources(device_t dev) /* Enable the ACPI bar */ acpi_cntl = pci_read_config8(dev, 0x44); - acpi_cntl |= (1 << 4); + acpi_cntl |= (1 << 7); pci_write_config8(dev, 0x44, acpi_cntl); /* Enable the GPIO bar */ |