diff options
| author | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:58:38 +0000 |
|---|---|---|
| committer | Sven Schnelle <svens@stackframe.org> | 2011-04-20 08:58:38 +0000 |
| commit | 81725b2effe9269e5079c6043077ba516e72aa82 (patch) | |
| tree | 36d93d3eaa95598bef4c64e6595aa454993cfa5e | |
| parent | 5c72a8752bb5ce1c3b1bfb77c08039c71c2113ef (diff) | |
| download | coreboot-81725b2effe9269e5079c6043077ba516e72aa82.tar.xz | |
pci1x2x: remove latency/bridge control/cacheline size settings
Those settings should be handled by the generic PCI/Cardbus code,
and not by the driver itself.
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Acked-by: Sven Schnelle <svens@stackframe.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
| -rw-r--r-- | src/mainboard/nokia/ip530/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/southbridge/ti/pci1x2x/chip.h | 3 | ||||
| -rw-r--r-- | src/southbridge/ti/pci1x2x/pci1x2x.c | 6 |
3 files changed, 0 insertions, 11 deletions
diff --git a/src/mainboard/nokia/ip530/devicetree.cb b/src/mainboard/nokia/ip530/devicetree.cb index a132604472..f89d1cd9fe 100644 --- a/src/mainboard/nokia/ip530/devicetree.cb +++ b/src/mainboard/nokia/ip530/devicetree.cb @@ -33,8 +33,6 @@ chip northbridge/intel/i440bx # Northbridge device pci 00.0 on subsystemid 0x13b8 0x0000 end - register "cltr" = "0x40" - register "bcr" = "0x7c0" register "scr" = "0x08449060" register "mrr" = "0x00007522" end diff --git a/src/southbridge/ti/pci1x2x/chip.h b/src/southbridge/ti/pci1x2x/chip.h index b40194e328..4c3676153d 100644 --- a/src/southbridge/ti/pci1x2x/chip.h +++ b/src/southbridge/ti/pci1x2x/chip.h @@ -6,8 +6,5 @@ extern struct chip_operations southbridge_ti_pci1x2x_ops; struct southbridge_ti_pci1x2x_config { int scr; int mrr; - int clsr; - int cltr; - int bcr; }; #endif diff --git a/src/southbridge/ti/pci1x2x/pci1x2x.c b/src/southbridge/ti/pci1x2x/pci1x2x.c index dfb183cd27..e59be4fd2c 100644 --- a/src/southbridge/ti/pci1x2x/pci1x2x.c +++ b/src/southbridge/ti/pci1x2x/pci1x2x.c @@ -34,12 +34,6 @@ static void ti_pci1x2y_init(struct device *dev) struct southbridge_ti_pci1x2x_config *conf = dev->chip_info; if (conf) { - /* Cache Line Size (offset 0x0C) */ - pci_write_config8(dev, 0x0C, conf->clsr); - /* CardBus latency timer (offset 0x1B) */ - pci_write_config8(dev, 0x1B, conf->cltr); - /* Bridge control (offset 0x3E) */ - pci_write_config16(dev, 0x3E, conf->bcr); /* System control (offset 0x80) */ pci_write_config32(dev, 0x80, conf->scr); /* Multifunction routing */ |