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authorPatrick Rudolph <patrick.rudolph@9elements.com>2019-05-20 10:05:18 +0200
committerPatrick Rudolph <siro@das-labor.org>2019-05-23 06:19:36 +0000
commit84b8f90bba65c56c4122d0a214608ef4e882861c (patch)
treee2f34466fbfff9cfa6b9416d8fb8585ec62ee073
parent239b13ce38e9f7edd86193a5edddb403cdac437d (diff)
downloadcoreboot-84b8f90bba65c56c4122d0a214608ef4e882861c.tar.xz
mb/asus/p8h61-m_pro: Add small fixes
* Add VBT * Configure OnBoard NIC * Add documentation Change-Id: Iad739b4e1dacb41f5f63247150951df7013bbf0c Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-rw-r--r--Documentation/mainboard/asus/p8h61-m_pro.jpgbin0 -> 69452 bytes
-rw-r--r--Documentation/mainboard/asus/p8h61-m_pro.md103
-rw-r--r--Documentation/mainboard/index.md1
-rw-r--r--src/mainboard/asus/p8h61-m_pro/Kconfig3
-rw-r--r--src/mainboard/asus/p8h61-m_pro/data.vbtbin0 -> 3902 bytes
-rw-r--r--src/mainboard/asus/p8h61-m_pro/devicetree.cb8
6 files changed, 114 insertions, 1 deletions
diff --git a/Documentation/mainboard/asus/p8h61-m_pro.jpg b/Documentation/mainboard/asus/p8h61-m_pro.jpg
new file mode 100644
index 0000000000..f3d60071b5
--- /dev/null
+++ b/Documentation/mainboard/asus/p8h61-m_pro.jpg
Binary files differ
diff --git a/Documentation/mainboard/asus/p8h61-m_pro.md b/Documentation/mainboard/asus/p8h61-m_pro.md
new file mode 100644
index 0000000000..169678efcd
--- /dev/null
+++ b/Documentation/mainboard/asus/p8h61-m_pro.md
@@ -0,0 +1,103 @@
+# ASUS P8H61-M Pro
+
+This page describes how to run coreboot on the [ASUS P8H61-M Pro].
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+------------+
+| Type | Value |
++=====================+============+
+| Socketed flash | yes |
++---------------------+------------+
+| Model | W25Q32BV |
++---------------------+------------+
+| Size | 4 MiB |
++---------------------+------------+
+| Package | DIP-8 |
++---------------------+------------+
+| Write protection | no |
++---------------------+------------+
+| Dual BIOS feature | no |
++---------------------+------------+
+| Internal flashing | yes |
++---------------------+------------+
+```
+
+The flash IC is located right next to one of the SATA ports:
+![](p8h61-m_pro.jpg)
+
+### Internal programming
+
+The main SPI flash can be accessed using [flashrom]. By default, only
+the BIOS region of the flash is writable. If you wish to change any
+other region (Management Engine or flash descriptor), then an external
+programmer is required.
+
+The following command may be used to flash coreboot:
+
+```
+$ sudo flashrom --noverify-all --ifd -i bios -p internal -w coreboot.rom
+```
+
+The use of `--noverify-all` is required since the Management Engine
+region is not readable even by the host.
+
+## Known issues
+
+- There is no automatic, OS-independent fan control. This is because
+ the super I/O hardware monitor can only obtain valid CPU temperature
+ readings from the PECI agent, whose complete initialisation is not
+ publicly documented. The `coretemp` driver can still be used for
+ accurate CPU temperature readings.
+
+- me_cleaner breaks LPC bus and attached components!
+- PS/2 mouse doesn't work
+
+## Untested
+
+- parallel port
+- EHCI debug
+- S/PDIF audio
+
+## Working
+
+- PS/2 keyboard
+- PCIe graphics
+- USB
+- Gigabit Ethernet
+- Integrated graphics
+- SATA
+- Serial port
+- hardware monitor (see [Known issues](#known-issues) for caveats)
+- front panel audio
+- Native raminit (2 x 2GB, DDR3-1333)
+- Native graphics init (libgfxinit)
+- Wake-on-LAN
+- TPM on TPM-header
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge | bd82x6x |
++------------------+--------------------------------------------------+
+| CPU | model_206ax |
++------------------+--------------------------------------------------+
+| Super I/O | Nuvoton NCT6776 |
++------------------+--------------------------------------------------+
+| EC | None |
++------------------+--------------------------------------------------+
+| Coprocessor | Intel Management Engine |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q32BV]
+
+[ASUS P8H61-M Pro]: https://www.asus.com/Motherboards/P8H61M_Pro/
+[W25Q32BV]: https://www.winbond.com/resource-files/w25q32bv_revi_100413_wo_automotive.pdf
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index eced74966e..1494e06244 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -6,6 +6,7 @@ This section contains documentation about coreboot on specific mainboards.
- [F2A85-M](asus/f2a85-m.md)
- [P8H61-M LX](asus/p8h61-m_lx.md)
+- [P8H61-M Pro](asus/p8h61-m_pro.md)
## ASRock
diff --git a/src/mainboard/asus/p8h61-m_pro/Kconfig b/src/mainboard/asus/p8h61-m_pro/Kconfig
index 14f841e649..e8a6f6404a 100644
--- a/src/mainboard/asus/p8h61-m_pro/Kconfig
+++ b/src/mainboard/asus/p8h61-m_pro/Kconfig
@@ -31,6 +31,9 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_CMOS_DEFAULT
select DRIVERS_ASMEDIA_ASPM_BLACKLIST
select MAINBOARD_HAS_LPC_TPM
+ select REALTEK_8168_RESET
+ select RT8168_SET_LED_MODE
+ select INTEL_GMA_HAVE_VBT
config MAINBOARD_DIR
string
diff --git a/src/mainboard/asus/p8h61-m_pro/data.vbt b/src/mainboard/asus/p8h61-m_pro/data.vbt
new file mode 100644
index 0000000000..114a840660
--- /dev/null
+++ b/src/mainboard/asus/p8h61-m_pro/data.vbt
Binary files differ
diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
index f853452728..d3f1795f91 100644
--- a/src/mainboard/asus/p8h61-m_pro/devicetree.cb
+++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb
@@ -49,7 +49,13 @@ chip northbridge/intel/sandybridge
device pci 1b.0 on end # High Definition Audio Audio controller
device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1)
device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2)
- device pci 1c.2 on end # Realtek RTL8111E Ethernet Controller
+ device pci 1c.2 on # Realtek RTL8111E Ethernet Controller
+ chip drivers/net
+ register "customized_leds" = "0x00f6"
+ register "wake" = "9"
+ device pci 00.0 on end
+ end
+ end
device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller
device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2)
device pci 1c.5 on end # ASMedia ASM1062 SATA Controller