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| author | Furquan Shaikh <furquan@google.com> | 2020-04-21 23:19:52 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-04-25 05:56:17 +0000 |
| commit | 8ebbe17b8613c9cf499ab7d5090ed4ee3356c1f9 (patch) | |
| tree | 12c32180f8af59ab1aa4db01a3e53182f86d8f51 | |
| parent | 5d76958de124af3877f9b399a4ec8a6377fe4ffd (diff) | |
| download | coreboot-8ebbe17b8613c9cf499ab7d5090ed4ee3356c1f9.tar.xz | |
soc/intel/tigerlake: Fix FSP SPD index for DDR4
For DDR4, FSP expects channel 0 to set SPD for index 0 and channel 1
to set SPD for index 4. This change adds a helper macro to translate
DDR4 channel # to the index # that the FSP expects.
BUG=b:154445630
TEST=Verified that memory initialization for DDR4 is successful.
Change-Id: I2b6ea2433453a574970c1c33ff629fd54ff5d508
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
| -rw-r--r-- | src/soc/intel/tigerlake/meminit.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index 86645472aa..d44554af7e 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -16,6 +16,14 @@ #define LPDDR4X_CHANNEL_UNPOPULATED(ch, half_populated) \ ((half_populated) && ((ch) >= (LPDDR4X_CHANNELS / 2))) +/* + * Translate DDR4 channel # to FSP UPD index # for the channel. + * Channel 0 -> Index 0 + * Channel 1 -> Index 4 + * Index 1-3 and 5-7 are unused. + */ +#define DDR4_FSP_UPD_CHANNEL_IDX(x) ((x) * 4) + enum dimm_enable_options { ENABLE_BOTH_DIMMS = 0, DISABLE_DIMM0 = 1, @@ -378,7 +386,7 @@ void meminit_ddr4(FSP_M_CONFIG *mem_cfg, const struct mb_ddr4_cfg *board_cfg, for (i = 0; i < DDR4_CHANNELS; i++) { ddr4_get_spd(i, &spd_md_data, &spd_sodimm_blk, info, half_populated, &spd_dimm0, &spd_dimm1); - init_spd_upds(mem_cfg, i, spd_dimm0, spd_dimm1); + init_spd_upds(mem_cfg, DDR4_FSP_UPD_CHANNEL_IDX(i), spd_dimm0, spd_dimm1); } /* |