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authorTimothy Pearson <tpearson@raptorengineering.com>2017-01-09 14:19:37 -0600
committerTimothy Pearson <tpearson@raptorengineering.com>2017-01-11 00:18:09 +0100
commit8fa624784e3d78e67cf7b4e0e72cb2208c399f0f (patch)
tree78cd839a8f5e461470b2a28c7294cc587630fa44
parentbc44178f0240fe2e6165f300674e3e74a021a0b9 (diff)
downloadcoreboot-8fa624784e3d78e67cf7b4e0e72cb2208c399f0f.tar.xz
amd/mct/ddr3: Correctly program maximum read latency
The existing code inadvertently calculated the maximum read latency for nonexistent channel 2 instead of for channels 0 and 1 as intended. Fix the calls to the maximum read latency training function. Found-by: Coverity Scan #1347354 Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18072 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
-rw-r--r--src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index fd8a8e76af..984f604135 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -1484,8 +1484,9 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
}
}
- /* Calculate and program MaxRdLatency */
- Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, Channel, 0);
+ /* Calculate and program MaxRdLatency for both channels */
+ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 0, 0);
+ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, 1, 0);
if (_DisableDramECC) {
mct_EnableDimmEccEn_D(pMCTstat, pDCTstat, _DisableDramECC);