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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-03-01 17:16:06 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-03-01 17:16:06 +0000
commit9d24c7f202c4ff353a8a97e955ee68ed340a98b1 (patch)
treeaf95887035012a8703fbcfbd0db03603e0474ad4
parentd3b2bbe08c59e36488ca9d04d01ddd61c04504ca (diff)
downloadcoreboot-9d24c7f202c4ff353a8a97e955ee68ed340a98b1.tar.xz
- Simplify stack size determination: MAX_CPUS * STACK_SIZE
- Check that this doesn't run into vga/oprom/bios area at link time - Avoid overly complicated and not well understood hack which avoids that area by leaving a hole in the stack area. - Adapt technexion/tim5690 to put ramstage at 1MB Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/arch/i386/coreboot_ram.ld8
-rw-r--r--src/cpu/x86/lapic/lapic_cpu_init.c18
-rw-r--r--src/mainboard/technexion/tim5690/Kconfig2
3 files changed, 7 insertions, 21 deletions
diff --git a/src/arch/i386/coreboot_ram.ld b/src/arch/i386/coreboot_ram.ld
index 2b603ea796..3915f31fd0 100644
--- a/src/arch/i386/coreboot_ram.ld
+++ b/src/arch/i386/coreboot_ram.ld
@@ -100,11 +100,11 @@ SECTIONS
_ebss = .;
_end = .;
. = ALIGN(CONFIG_STACK_SIZE);
+
_stack = .;
.stack . : {
/* Reserve a stack for each possible cpu */
- /* the stack for ap will be put after pgtbl in 1M to CONFIG_RAMTOP range when VGA and ROM_RUN and CONFIG_RAMTOP>1M*/
- . += ((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN)&&(CONFIG_RAMBASE<0x100000)&&(CONFIG_RAMTOP>0x100000) ) ? CONFIG_STACK_SIZE : (CONFIG_MAX_CPUS*CONFIG_STACK_SIZE);
+ . += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE;
}
_estack = .;
_heap = .;
@@ -114,6 +114,10 @@ SECTIONS
. = ALIGN(4);
}
_eheap = .;
+
+ /* Avoid running into 0xa0000-0xfffff */
+ _bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB");
+
/* The ram segment
* This is all address of the memory resident copy of coreboot.
*/
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 2e938eeaaf..3033902525 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -246,25 +246,7 @@ int start_cpu(device_t cpu)
index = ++last_cpu_index;
/* Find end of the new processors stack */
-#if (CONFIG_RAMTOP>0x100000) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
- if(index<1) { // only keep bsp on low
- stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
- } else {
- // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
- stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
-#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_RAMTOP)
- #warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
-#endif
- if(stack_end > (CONFIG_RAMTOP)) {
- printk_debug("start_cpu: Please increase the CONFIG_RAMTOP more than %luK\n", stack_end);
- die("Can not go on\n");
- }
- stack_end -= sizeof(struct cpu_info);
- }
-#else
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
-#endif
-
/* Record the index and which cpu structure we are using */
info = (struct cpu_info *)stack_end;
diff --git a/src/mainboard/technexion/tim5690/Kconfig b/src/mainboard/technexion/tim5690/Kconfig
index b2b4362874..b8d73f1de4 100644
--- a/src/mainboard/technexion/tim5690/Kconfig
+++ b/src/mainboard/technexion/tim5690/Kconfig
@@ -127,5 +127,5 @@ config HEAP_SIZE
config RAMBASE
hex
- default 0x4000
+ default 0x100000
depends on BOARD_TECHNEXION_TIM5690