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authorAaron Durbin <adurbin@chromium.org>2016-09-13 12:31:57 -0500
committerAaron Durbin <adurbin@chromium.org>2016-09-14 15:40:16 +0200
commit9e81540b85c6d06c7c3c63447b92f09590f032d1 (patch)
tree34e120d03c5c03bd6af4181f05e42b92202a58ce
parent9a23569ee14f828f950516bb71ec7eab99521b61 (diff)
downloadcoreboot-9e81540b85c6d06c7c3c63447b92f09590f032d1.tar.xz
soc/intel/apollolake: initialize GNVS structure to 0
The code was not previously initializing the GNVS structure to all 0's in the ACPI write tables path. Fix this and also rearrange the ordering of updating the fields to only handle the chip_info specific bits till last such that most of the structure is filled in prior to bailing out in the case of a bad devicetree. Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16597 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
-rw-r--r--src/soc/intel/apollolake/acpi.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 4f4276ad72..1ca04fd3fe 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -28,6 +28,7 @@
#include <soc/pm.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
+#include <string.h>
#include "chip.h"
#define CSTATE_RES(address_space, width, offset, address) \
@@ -151,11 +152,8 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
struct soc_intel_apollolake_config *cfg;
struct device *dev = NB_DEV_ROOT;
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
- return;
- }
- cfg = dev->chip_info;
+ /* Clear out GNVS. */
+ memset(gnvs, 0, sizeof(*gnvs));
if (IS_ENABLED(CONFIG_CONSOLE_CBMEM))
gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
@@ -166,11 +164,17 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
}
- /* Enable DPTF based on mainboard configuration */
- gnvs->dpte = cfg->dptf_enable;
-
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
+ return;
+ }
+ cfg = dev->chip_info;
+
+ /* Enable DPTF based on mainboard configuration */
+ gnvs->dpte = cfg->dptf_enable;
}
/* Save wake source information for calculating ACPI _SWS values */