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authorPatrick Rudolph <siro@das-labor.org>2015-08-17 19:24:12 +0200
committerNico Huber <nico.h@gmx.de>2015-11-18 15:08:51 +0100
commit9f1fbb9a3002e8d74d53d7973bd1c7e3d4879238 (patch)
treeaf127d6ef46570f46ba04febe8dc3e547938c4c7
parent7dcf9d51e5ffadfcf8b5fceddcddb4e1d0a7db37 (diff)
downloadcoreboot-9f1fbb9a3002e8d74d53d7973bd1c7e3d4879238.tar.xz
northbridge/intel/sandybridge: Fix random raminit failures
Issue observed: Intel raminit works in about 50% of all test-cases on lenovo x220. Problem solution: Prefer a smaller valid value over the measured one for initial timB timings. Final testing result: Tests on x220 shows that the issue was resolved. The test system booted successfully ten times in a row. Tests on Gigabyte GA-B75M-D3H revealed no regressions. Test system: * Intel Pentium CPU G2130 * Gigabyte GA-B75M-D3H * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ" Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11248 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 01ad3ed9d2..fa71bc10d3 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -2262,7 +2262,17 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
}
FOR_ALL_LANES {
struct run rn = get_longest_zero_run(statistics[lane], 128);
- ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
+ if (rn.start < rn.middle) {
+ ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
+ } else {
+ /* In this case statistics[lane][7f] and statistics[lane][0] are
+ * both zero.
+ * Prefer a smaller value over rn.start to prevent failures in
+ * the following write tests.
+ */
+ ctrl->timings[channel][slotrank].lanes[lane].timB = 0;
+ }
+
if (rn.all)
die("timB discovery failed");
printram("Bval: %d, %d, %d, %x\n", channel, slotrank,