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authorMaxim Polyakov <max.senia.poliak@gmail.com>2019-08-21 16:29:07 +0300
committerPatrick Georgi <pgeorgi@google.com>2019-09-09 13:27:50 +0000
commita433da754ab42083d1885d60bb819a28728e3b29 (patch)
tree6b75470ec752ca7492d2d22ddf150cf65cabb56d
parent21353baa16b74a5ea46d34bf9388adb0c3b4b8c1 (diff)
downloadcoreboot-a433da754ab42083d1885d60bb819a28728e3b29.tar.xz
mb/asrock/h110m: disable unused serial buses
Disable spi0, i2c0 and i2c1 in the “SerialIoDevMode” register for the following reasons: 1. when the AMI BIOS is used, these pci devices are disabled in lspci.log; 2. there are no pads in the inteltool.log that use the functions of these buses Change-Id: I01ab10eb3fd41e81a1726805247c2b472d72287c Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35070 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/asrock/h110m/devicetree.cb6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 60a3aaa0c4..47d534a99b 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -190,13 +190,13 @@ chip soc/intel/skylake
# PCH UART, SPI, I2C
register "SerialIoDevMode" = "{ \
- [PchSerialIoIndexI2C0] = PchSerialIoPci, \
- [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C1] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C4] = PchSerialIoDisabled, \
[PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
- [PchSerialIoIndexSpi0] = PchSerialIoPci, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
[PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
[PchSerialIoIndexUart0] = PchSerialIoDisabled, \
[PchSerialIoIndexUart1] = PchSerialIoDisabled, \