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authorBarnali Sarkar <barnali.sarkar@intel.com>2016-11-28 14:53:12 +0530
committerAaron Durbin <adurbin@chromium.org>2016-11-30 17:03:44 +0100
commita5b10417e41267e34126b806ae7653c488217ad5 (patch)
treee303520cc8a093059e6613c613a127983b7c4139
parentd138871b16b85ff04c045ab7b11e4b2db87a09bf (diff)
downloadcoreboot-a5b10417e41267e34126b806ae7653c488217ad5.tar.xz
mb/intel/kblrvp: Add Variant board support for KBLRVP
Add support of Variant board model for existing intel/kblrvp, since there might be more RVP board supports under intel/kblrvp. Existing is for KBL RVP3 board. BUG=none BRANCH=none TEST=Built and boot Kaby Lake RVP3 Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/17630 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
-rw-r--r--src/Kconfig2
-rw-r--r--src/mainboard/intel/kblrvp/Kconfig8
-rw-r--r--src/mainboard/intel/kblrvp/Makefile.inc3
-rw-r--r--src/mainboard/intel/kblrvp/acpi/ec.asl2
-rw-r--r--src/mainboard/intel/kblrvp/acpi/mainboard.asl2
-rw-r--r--src/mainboard/intel/kblrvp/bootblock.c2
-rw-r--r--src/mainboard/intel/kblrvp/mainboard.c2
-rw-r--r--src/mainboard/intel/kblrvp/ramstage.c2
-rw-r--r--src/mainboard/intel/kblrvp/smihandler.c2
-rw-r--r--src/mainboard/intel/kblrvp/spd/spd.h3
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb (renamed from src/mainboard/intel/kblrvp/devicetree.cb)0
-rw-r--r--src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h (renamed from src/mainboard/intel/kblrvp/gpio.h)0
12 files changed, 19 insertions, 9 deletions
diff --git a/src/Kconfig b/src/Kconfig
index 77d13d1db8..5cd02542ea 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -326,7 +326,7 @@ config GENERIC_SPD_BIN
config DIMM_MAX
int
- default 2
+ default 4
depends on GENERIC_SPD_BIN
help
Total number of memory DIMM slots available on motherboard.
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
index e53c4465db..10752e76f9 100644
--- a/src/mainboard/intel/kblrvp/Kconfig
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -48,6 +48,10 @@ config MAINBOARD_DIR
string
default "intel/kblrvp"
+config VARIANT_DIR
+ string
+ default "rvp3"
+
config MAINBOARD_PART_NUMBER
string
default "Kblrvp"
@@ -68,4 +72,8 @@ config GBB_HWID
string
depends on CHROMEOS
default "KBLRVP TEST 8819"
+
+config DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
endif
diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc
index 68c87c9ca6..7ddfb9fa91 100644
--- a/src/mainboard/intel/kblrvp/Makefile.inc
+++ b/src/mainboard/intel/kblrvp/Makefile.inc
@@ -32,3 +32,6 @@ ramstage-y += mainboard.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl
index 7d7ff2ffa8..01fa75c6ff 100644
--- a/src/mainboard/intel/kblrvp/acpi/ec.asl
+++ b/src/mainboard/intel/kblrvp/acpi/ec.asl
@@ -15,7 +15,7 @@
/* mainboard configuration */
#include "../ec.h"
-#include "../gpio.h"
+#include <variant/gpio.h>
/* Enable EC backed ALS device in ACPI */
#define EC_ENABLE_ALS_DEVICE
diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
index 5d2b3071b5..4764372778 100644
--- a/src/mainboard/intel/kblrvp/acpi/mainboard.asl
+++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
@@ -14,7 +14,7 @@
* GNU General Public License for more details.
*/
-#include "../gpio.h"
+#include <variant/gpio.h>
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)
Scope (\_SB)
diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c
index 627b4e8b08..dde7e8612a 100644
--- a/src/mainboard/intel/kblrvp/bootblock.c
+++ b/src/mainboard/intel/kblrvp/bootblock.c
@@ -15,7 +15,7 @@
#include <bootblock_common.h>
#include <soc/gpio.h>
-#include "gpio.h"
+#include <variant/gpio.h>
static void early_config_gpio(void)
{
diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c
index cd6c3f90be..652af732de 100644
--- a/src/mainboard/intel/kblrvp/mainboard.c
+++ b/src/mainboard/intel/kblrvp/mainboard.c
@@ -24,7 +24,7 @@
#include <soc/nhlt.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include "ec.h"
-#include "gpio.h"
+#include <variant/gpio.h>
static void mainboard_init(device_t dev)
{
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
index bcd72bc41e..3a48396d22 100644
--- a/src/mainboard/intel/kblrvp/ramstage.c
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -17,7 +17,7 @@
#include <console/console.h>
#include <device/i2c.h>
#include <soc/ramstage.h>
-#include "gpio.h"
+#include <variant/gpio.h>
void mainboard_silicon_init_params(FSP_SIL_UPD *params)
{
diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c
index 81aaf23b64..9ecc43aaff 100644
--- a/src/mainboard/intel/kblrvp/smihandler.c
+++ b/src/mainboard/intel/kblrvp/smihandler.c
@@ -25,7 +25,7 @@
#include <soc/pm.h>
#include <soc/smm.h>
#include "ec.h"
-#include "gpio.h"
+#include <variant/gpio.h>
int mainboard_io_trap_handler(int smif)
{
diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h
index 3ef2dd848c..c24baa07bf 100644
--- a/src/mainboard/intel/kblrvp/spd/spd.h
+++ b/src/mainboard/intel/kblrvp/spd/spd.h
@@ -18,8 +18,7 @@
#define MAINBOARD_SPD_H
#include <gpio.h>
-#include "../gpio.h"
-
+#include <variant/gpio.h>
#define RCOMP_TARGET_PARAMS 0x5
diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
index c2dde4f526..c2dde4f526 100644
--- a/src/mainboard/intel/kblrvp/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb
diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h
index c6f41234ef..c6f41234ef 100644
--- a/src/mainboard/intel/kblrvp/gpio.h
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/include/variant/gpio.h