diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-08-18 10:07:07 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-10-16 00:12:48 +0000 |
| commit | a5f225f288a6f1bf1db0885bdc9635f2bf185374 (patch) | |
| tree | 513e581d518c83e27c09e3a9ada133281dce8c96 | |
| parent | 78130663e5cac7939ee04f97ac1c7fcecde23820 (diff) | |
| download | coreboot-a5f225f288a6f1bf1db0885bdc9635f2bf185374.tar.xz | |
soc/amd/stoneyridge: Check UART index
The Stoney Ridge APU has only two internal UARTs. Add checks for
invalid settings. When enabling the UART, return if the console is
on any UART not equal 0 or 1. The base address returned is 0 if an
invalid configuration is used. All callers check the return value
before using the returned value. Finally, provide an assert at the
earliest availability of the console to get the notice into the
cbmem console.
BUG=b:62201567
TEST=Build with UART = -1, 0, 2. Inspect objdump and boot to OS.
Build without ST UART and inspect with objdump.
Change-Id: I9432571712bae15a604f4280ea5e0f81fd68604d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | src/soc/amd/stoneyridge/bootblock/bootblock.c | 5 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/early_setup.c | 3 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/uart.c | 3 |
3 files changed, 11 insertions, 0 deletions
diff --git a/src/soc/amd/stoneyridge/bootblock/bootblock.c b/src/soc/amd/stoneyridge/bootblock/bootblock.c index 3f01603b14..1712b5159a 100644 --- a/src/soc/amd/stoneyridge/bootblock/bootblock.c +++ b/src/soc/amd/stoneyridge/bootblock/bootblock.c @@ -15,6 +15,7 @@ */ #include <stdint.h> +#include <assert.h> #include <console/console.h> #include <smp/node.h> #include <bootblock_common.h> @@ -52,6 +53,10 @@ void bootblock_soc_early_init(void) void bootblock_soc_init(void) { + if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) + assert(CONFIG_UART_FOR_CONSOLE >= 0 + && CONFIG_UART_FOR_CONSOLE <= 1); + u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); diff --git a/src/soc/amd/stoneyridge/early_setup.c b/src/soc/amd/stoneyridge/early_setup.c index e5f123a151..b4e780ece1 100644 --- a/src/soc/amd/stoneyridge/early_setup.c +++ b/src/soc/amd/stoneyridge/early_setup.c @@ -35,6 +35,9 @@ void configure_stoneyridge_uart(void) { u8 byte, byte2; + if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + return; + /* Power on the UART and AMBA devices */ byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); diff --git a/src/soc/amd/stoneyridge/uart.c b/src/soc/amd/stoneyridge/uart.c index 9cc0c94894..d5d30061bf 100644 --- a/src/soc/amd/stoneyridge/uart.c +++ b/src/soc/amd/stoneyridge/uart.c @@ -18,6 +18,9 @@ uintptr_t uart_platform_base(int idx) { + if (CONFIG_UART_FOR_CONSOLE < 0 || CONFIG_UART_FOR_CONSOLE > 1) + return 0; + return (uintptr_t)(APU_UART0_BASE + 0x2000 * (idx & 1)); } |