mb/google/volteer: sync'ing todor with terrador

Todor is created to take the place of terrador therefore
copying terrador content into todor's setup.

BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I63151728a04f2252ca8a77158a2656ad8b1e1b51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

10 files changed, 438 insertions, 17 deletions

diff --git a/src/mainboard/google/volteer/variants/todor/Makefile.inc b/src/mainboard/google/volteer/variants/todor/Makefile.inc
new file mode 100644
index 0000000000..b0bfc567ff
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/todor/Makefile.inc
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/volteer/variants/todor/gpio.c b/src/mainboard/google/volteer/variants/todor/gpio.c
new file mode 100644
index 0000000000..e49e2dccf5
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/todor/gpio.c
@@ -0,0 +1,229 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <variant/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config override_gpio_table[] = {
+	/* A7  : I2S2_SCLK ==> I2S1_SPKR_SCLK */
+	PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1),
+	/* A8  : I2S2_SFRM ==> I2S1_SPKR_SFRM */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+	/* A9  : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */
+	PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+	/* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */
+	PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
+	/* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* A16 : USB_OC3# ==> USB_C0_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A18 : DDSP_HPDB ==> HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A19 : DDSP_HPD1 ==> USB_C0_DP_HPD */
+	PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
+	/* A20 : DDSP_HPD2 ==> USB_C1_DP_HPD */
+	PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
+	/* A21 : DDPC_CTRCLK ==> EN_FP_PWR */
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+	/* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+
+	/* B2  : VRALERT# ==> NC */
+	PAD_NC(GPP_B2, NONE),
+	/* B7  : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+	/* B8  : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
+	/* B9  : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */
+	PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+	/* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+	/* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */
+	PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
+	/* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */
+	PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
+	/* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
+	/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
+	PAD_NC(GPP_B23, DN_20K),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, DN_20K),
+	/* C3  : SML0CLK ==> USB4_SMB_SCL */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+	/* C4  : SML0DATA ==> USB4_SMB_SDA */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+	/* C5  : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
+	PAD_NC(GPP_C5, DN_20K),
+	/* C7  : SML1DATA ==> EN_USI_CHARGE */
+	PAD_CFG_GPO(GPP_C7, 1, DEEP),
+	/* C10 : UART0_RTS# ==> USI_RST_L */
+	PAD_CFG_GPO(GPP_C10, 1, DEEP),
+	/* C13 : UART1_TXD ==> EN_PP5000_TRACKPAD */
+	PAD_CFG_GPO(GPP_C13, 1, DEEP),
+	/* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */
+	PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+	/* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */
+	PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+	/* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	/* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	/* C20 : UART2_RXD ==> FPMCU_INT_L */
+	PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL),
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+	/* C23 : UART2_CTS# ==> FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C23, 1, DEEP),
+
+	/* D0  : ISH_GP0 ==> ISH_IMU_INT_L */
+	PAD_CFG_GPI(GPP_D0, NONE, DEEP),
+	/* D1  : ISH_GP1 ==> ISH_ACCEL_INT_L */
+	PAD_CFG_GPI(GPP_D1, NONE, DEEP),
+	/* D2  : ISH_GP2 ==> ISH_LID_OPEN */
+	PAD_CFG_GPI(GPP_D2, NONE, DEEP),
+	/* D8  : SRCCLKREQ3# ==> SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */
+	PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7),
+	/* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */
+	PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7),
+	/* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+
+	/* E1  : SPI1_IO2 ==> PEN_DET_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+	/* E3  : CPU_GP0 ==> USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_E3, 1, DEEP),
+	/* E7  : CPU_GP1 ==> USI_INT */
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+	/* E10 : SPI1_CS# ==> NC */
+	PAD_NC(GPP_E10, NONE),
+	/* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E11, NONE, DEEP),
+	/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
+	PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+	/* E13 : SPI1_MOSI_IO0 ==> NC */
+	PAD_NC(GPP_E13, NONE),
+	/* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+	/* E16 : ISH_GP7 ==> USB_A0_RT_RST_ODL */
+	PAD_CFG_GPO(GPP_E16, 1, DEEP),
+	/* E17 : THC0_SPI1_INT# ==> PEN_DET_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+	/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
+	PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4),
+
+	/* F7  : GPPF7_STRAP */
+	PAD_NC(GPP_F7, DN_20K),
+	/* F11 : THC1_SPI2_CLK ==> NC */
+	PAD_NC(GPP_F11, NONE),
+	/* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */
+	PAD_CFG_GPO(GPP_F12, 1, DEEP),
+	/* F13 : GSXDOUT ==> WiFi_DISABLE_L */
+	PAD_CFG_GPO(GPP_F13, 1, DEEP),
+	/* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_F16, 1, DEEP),
+	/* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_F17, NONE, DEEP),
+	/* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */
+	PAD_CFG_GPO(GPP_F18, 1, DEEP),
+
+	/* H0  : GPPH0_BOOT_STRAP1 */
+	PAD_NC(GPP_H0, DN_20K),
+	/* H1  : GPPH1_BOOT_STRAP2 */
+	PAD_NC(GPP_H1, DN_20K),
+	/* H2  : GPPH2_BOOT_STRAP3 */
+	PAD_NC(GPP_H2, DN_20K),
+	/* H3  : SX_EXIT_HOLDOFF# ==> SD_PERST_L */
+	PAD_CFG_GPO(GPP_H3, 1, DEEP),
+	/* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_H10, 1, DEEP),
+	/* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */
+	PAD_CFG_GPI(GPP_H13, NONE, DEEP),
+	/* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+	/* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */
+	PAD_CFG_GPI(GPP_H19, NONE, DEEP),
+
+	/* R0 : HDA_BCLK ==> I2S0_HP_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : HDA_SYNC ==> I2S0_HP_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R5 : HDA_SDI1 ==> HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH),
+
+	/* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1),
+	/* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1),
+	/* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1),
+	/* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1),
+	/* S6 : SNDW3_CLK ==> DMIC_CLK0 */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* S7 : SNDW3_DATA ==> DMIC_DATA0 */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* GPD6: SLP_A# ==> NC */
+	PAD_NC(GPD6, NONE),
+	/* GPD9: SLP_WLAN# ==> SLP_WLAN_L */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_override_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(override_gpio_table);
+	return override_gpio_table;
+}
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+	/* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+
+	/* B11 : PMCALERT# ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+	/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
+	/* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+	/* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */
+	PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1),
+
+	/* C0  : SMBCLK ==> EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C21 : UART2_TXD ==> H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
+	/* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_C22, 0, DEEP),
+
+	/* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */
+	PAD_CFG_GPI(GPP_E12, NONE, DEEP),
+};
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
diff --git a/src/mainboard/google/volteer/variants/todor/include/variant/acpi/dptf.asl b/src/mainboard/google/volteer/variants/todor/include/variant/acpi/dptf.asl
deleted file mode 100644
index 189cafea4c..0000000000
--- a/src/mainboard/google/volteer/variants/todor/include/variant/acpi/dptf.asl
+++ /dev/null
@@ -1,3 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <baseboard/acpi/dptf.asl>
diff --git a/src/mainboard/google/volteer/variants/todor/include/variant/ec.h b/src/mainboard/google/volteer/variants/todor/include/variant/ec.h
index 7a2a6ff8b7..4a9a461191 100644
--- a/src/mainboard/google/volteer/variants/todor/include/variant/ec.h
+++ b/src/mainboard/google/volteer/variants/todor/include/variant/ec.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #ifndef __VARIANT_EC_H__
 #define __VARIANT_EC_H__
diff --git a/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h b/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h
index 419edcc42e..fe512d8c4a 100644
--- a/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h
+++ b/src/mainboard/google/volteer/variants/todor/include/variant/gpio.h
@@ -1,19 +1,12 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
- * GNU General Public License for more details.
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
+/* SPDX-License-Identifier: GPL-2.0-only */
 
 #ifndef VARIANT_GPIO_H
 #define VARIANT_GPIO_H
 
 #include <baseboard/gpio.h>
 
+#undef GPIO_EC_IN_RW
+/* EC in RW */
+#define GPIO_EC_IN_RW		GPP_F17
+
 #endif
diff --git a/src/mainboard/google/volteer/variants/todor/memory.c b/src/mainboard/google/volteer/variants/todor/memory.c
new file mode 100644
index 0000000000..5adf80cf81
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/todor/memory.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+
+static const struct lpddr4x_cfg todor_memcfg = {
+	/* DQ byte map */
+	.dq_map = {
+		[0] = {
+			{ 7,  3,  1,  4,  0,  5,  2,  6, }, /* DDR0_DQ0[7:0] */
+			{ 13, 14, 8,  10, 9,  15, 11, 12 }, /* DDR0_DQ1[7:0] */
+		},
+		[1] = {
+			{ 1,  2,  7,  6,  3,  5,  4,  0, }, /* DDR1_DQ0[7:0] */
+			{ 14, 15, 13, 10,  8, 11, 12, 9  }, /* DDR1_DQ1[7:0] */
+		},
+		[2] = {
+			{ 11, 15, 10, 9,  8, 12, 13, 14, }, /* DDR2_DQ0[7:0] */
+			{ 5,  6,  4,  0,  7,  2,  3,  1  }, /* DDR2_DQ1[7:0] */
+		},
+		[3] = {
+			{ 11, 15, 10, 9, 13, 12, 14,  8, }, /* DDR3_DQ0[7:0] */
+			{ 0,  5,  6,  4,  1,  2,  7,  3  }, /* DDR3_DQ1[7:0] */
+		},
+		[4] = {
+			{ 7,  2,  3,  1,  4,  0,  5,  6, }, /* DDR4_DQ0[7:0] */
+			{ 13, 14,  8, 12, 10,  9, 15, 11 }, /* DDR4_DQ1[7:0] */
+		},
+		[5] = {
+			{ 7,  3,  2,  1,  6,  4,  0,  5, }, /* DDR5_DQ0[7:0] */
+			{ 15, 14, 12, 8, 11, 13,  9,  10 }, /* DDR5_DQ1[7:0] */
+		},
+		[6] = {
+			{ 11, 10, 15, 12, 8,  9, 14, 13, }, /* DDR6_DQ0[7:0] */
+			{ 6,  0,  5,  4,  3,  2,  7,  1  }, /* DDR6_DQ1[7:0] */
+		},
+		[7] = {
+			{ 9, 10, 11,  8, 12, 14, 13, 15, }, /* DDR7_DQ0[7:0] */
+			{ 0,  5,  4,  7,  1,  6,  3,  2  }, /* DDR7_DQ1[7:0] */
+		},
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+		[0] = { 0, 1 },  /* DDR0_DQS[1:0] */
+		[1] = { 0, 1 },  /* DDR1_DQS[1:0] */
+		[2] = { 1, 0 },  /* DDR2_DQS[1:0] */
+		[3] = { 1, 0 },  /* DDR3_DQS[1:0] */
+		[4] = { 0, 1 },  /* DDR4_DQS[1:0] */
+		[5] = { 0, 1 },  /* DDR5_DQS[1:0] */
+		[6] = { 1, 0 },  /* DDR6_DQS[1:0] */
+		[7] = { 1, 0 },  /* DDR7_DQS[1:0] */
+	},
+
+	.ect = 1, /* Enable Early Command Training */
+};
+
+const struct lpddr4x_cfg *variant_memory_params(void)
+{
+	return &todor_memcfg;
+}
diff --git a/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc b/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc
new file mode 100644
index 0000000000..fc2631cab7
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/todor/memory/Makefile.inc
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+
+SPD_SOURCES =
+SPD_SOURCES += spd-1.hex      # ID = 0(0b0000)  Parts = MT53E512M64D4NW-046 WT:E
+SPD_SOURCES += spd-3.hex      # ID = 1(0b0001)  Parts = MT53E1G64D8NW-046 WT:E
diff --git a/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt
new file mode 100644
index 0000000000..02e7443467
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/todor/memory/dram_id.generated.txt
@@ -0,0 +1,3 @@
+DRAM Part Name                 ID to assign
+MT53E512M64D4NW-046 WT:E       0 (0000)
+MT53E1G64D8NW-046 WT:E         1 (0001)
diff --git a/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt
new file mode 100644
index 0000000000..b74da4a5f0
--- /dev/null
+++ b/src/mainboard/google/volteer/variants/todor/memory/mem_list_variant.txt
@@ -0,0 +1,2 @@
+MT53E512M64D4NW-046 WT:E
+MT53E1G64D8NW-046 WT:E
diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb
index 32204c58e7..c1c386a621 100644
--- a/src/mainboard/google/volteer/variants/todor/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb
@@ -1,6 +1,130 @@
 chip soc/intel/tigerlake
+	# BitMask where bits [3:0] are Controller 0 Channel [3:0] and
+	# bits [7:4] are Controller 1 Channel [3:0].
+	# Enable Command Mirroring for controller 0 channel 0 and 1,
+	# and controller 1 channel 0 and 1.
+	register "CmdMirror" = "0x00000033"
+
+	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
+	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
+	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"	# Type-A / Type-C Port 1
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)"	# Front Camera
+	register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC0)"	# Type-A / Type-C Port 0
+	register "usb2_ports[5]" = "USB2_PORT_EMPTY"		# Type-A / Type-C Not Used
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"	# Type-A / Type-C Port 0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)"	# Type-A / Type-C Port 1
+	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
+	register "usb3_ports[3]" = "USB3_PORT_EMPTY"		# Type-A / Type-C Not Used
+
+	register "SaGv" = "SaGv_Disabled"
 
 	device domain 0 on
+		device pci 15.0 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on
+				end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "0"
+				register "imon_slot_no" = "1"
+				register "uid" = "0"
+				register "desc" = ""Right Speaker Amp""
+				register "name" = ""MAXR""
+				device i2c 31 on
+				end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "2"
+				register "imon_slot_no" = "3"
+				register "uid" = "1"
+				register "desc" = ""Left Speaker Amp""
+				register "name" = ""MAXL""
+				device i2c 32 on
+				end
+			end
+		end # I2C #0			0xA0E8
+		device pci 15.1 on
+			chip drivers/i2c/hid
+				register "generic.hid" = ""GDIX0000""
+				register "generic.desc" = ""Goodix Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+				register "generic.reset_delay_ms" = "120"
+				register "generic.reset_off_delay_ms" = "3"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+				register "generic.enable_delay_ms" = "12"
+				register "generic.has_power_resource" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 14 on end
+			end
+			chip drivers/i2c/hid
+				register "generic.hid" = ""ELAN90FC""
+				register "generic.desc" = ""ELAN Touchscreen""
+				register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
+				register "generic.probed" = "1"
+				register "generic.reset_gpio" =
+							"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
+				register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
+				register "generic.reset_delay_ms" = "20"
+				register "generic.has_power_resource" = "1"
+				register "generic.disable_gpio_export_in_crs" = "1"
+				register "hid_desc_reg_offset" = "0x01"
+				device i2c 10 on end
+			end
+		end # I2C1				0xA0E9
+		device pci 15.2 on
+			chip drivers/i2c/sx9310
+				register "desc" = ""SAR0 Proximity Sensor""
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)"
+				register "speed" = "I2C_SPEED_FAST"
+				register "uid" = "0"
+				register "reg_prox_ctrl0" = "0x10"
+				register "reg_prox_ctrl1" = "0x00"
+				register "reg_prox_ctrl2" = "0x84"
+				register "reg_prox_ctrl3" = "0x0e"
+				register "reg_prox_ctrl4" = "0x07"
+				register "reg_prox_ctrl5" = "0xc6"
+				register "reg_prox_ctrl6" = "0x20"
+				register "reg_prox_ctrl7" = "0x0d"
+				register "reg_prox_ctrl8" = "0x8d"
+				register "reg_prox_ctrl9" = "0x43"
+				register "reg_prox_ctrl10" = "0x1f"
+				register "reg_prox_ctrl11" = "0x00"
+				register "reg_prox_ctrl12" = "0x00"
+				register "reg_prox_ctrl13" = "0x00"
+				register "reg_prox_ctrl14" = "0x00"
+				register "reg_prox_ctrl15" = "0x00"
+				register "reg_prox_ctrl16" = "0x00"
+				register "reg_prox_ctrl17" = "0x00"
+				register "reg_prox_ctrl18" = "0x00"
+				register "reg_prox_ctrl19" = "0x00"
+				register "reg_sar_ctrl0" = "0x50"
+				register "reg_sar_ctrl1" = "0x8a"
+				register "reg_sar_ctrl2" = "0x3c"
+				device i2c 28 on end
+			end
+		end # I2C2				0xA0EA
+		device pci 19.1 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end # I2C5				0xA0C6
 	end
-
 end