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| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-07-06 15:27:27 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-19 16:16:44 +0000 |
| commit | acfc149f7b16ef40816e3d5d4c2f8452fe9dd091 (patch) | |
| tree | aa0fe466beffbe71b9912d677fd3fa2864f88ec7 | |
| parent | 6228b9efb7f2fda1d248fb2fa320bf8cf2da55f8 (diff) | |
| download | coreboot-acfc149f7b16ef40816e3d5d4c2f8452fe9dd091.tar.xz | |
soc/intel/cannonlake: Add microcode support
Microcode needs to be loaded prior to FSP initialization.
Change-Id: Idd70bd3e6555866d9bb232e8904aed4120c79fe7
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20484
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/soc/intel/cannonlake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/Makefile.inc | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index b3f657e0bd..2c60309e6d 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select UDELAY_TSC select REG_SCRIPT select C_ENVIRONMENT_BOOTBLOCK + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE select INTEL_CAR_NEM_ENHANCED @@ -36,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_GPIO + select SUPPORT_CPU_UCODE_IN_CBFS config UART_DEBUG bool "Enable UART debug port." diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 8afd7ce306..27c2e9b864 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -1,5 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_CANNONLAKE),y) +subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/tsc |