mb/google/auron: Convert variants to use override devicetree

Since the variants' devicetrees are almost identical, convert to
using an overridetree setup for simplicity.

As part of the cleanup, drop unused PCIe RP5 for buddy as well.

Test: build all auron variants, compare generated static.c to ensure
resulting generated contents unchanged (although layout will)

Change-Id: I290e7243335a64afdcfc629db7b8ce18f5aa993c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

13 files changed, 158 insertions, 554 deletions

diff --git a/src/mainboard/google/auron/Kconfig b/src/mainboard/google/auron/Kconfig
index 644104a37e..20d2e440c2 100644
--- a/src/mainboard/google/auron/Kconfig
+++ b/src/mainboard/google/auron/Kconfig
@@ -48,9 +48,9 @@ config MAINBOARD_PART_NUMBER
 	default "Lulu" if BOARD_GOOGLE_LULU
 	default "Samus" if BOARD_GOOGLE_SAMUS
 
-config DEVICETREE
+config OVERRIDE_DEVICETREE
 	string
-	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+	default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
 
 config EC_GOOGLE_CHROMEEC_BOARDNAME
 	string
diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/devicetree.cb
index f6ec15a617..cabcdf0c4b 100644
--- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb
+++ b/src/mainboard/google/auron/devicetree.cb
@@ -12,14 +12,6 @@ chip soc/intel/broadwell
 	# Set backlight PWM value for eDP
 	register "gpu_pch_backlight_pwm_hz" = "200"
 
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
-	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
-	register "gpu_panel_power_up_delay" = "400"		# 40ms
-	register "gpu_panel_power_down_delay" = "150"		# 15ms
-	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
-
 	register "pirqa_routing" = "0x8b"
 	register "pirqb_routing" = "0x8a"
 	register "pirqc_routing" = "0x8b"
@@ -44,10 +36,6 @@ chip soc/intel/broadwell
 	register "sata_port_map" = "0x1"
 	register "sio_acpi_mode" = "1"
 
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
-
 	# Force enable ASPM for PCIe Port1
 	register "pcie_port_force_aspm" = "0x01"
 
@@ -61,32 +49,32 @@ chip soc/intel/broadwell
 	end
 
 	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
+		device pci 00.0 on  end # host bridge
+		device pci 02.0 on  end # vga controller
+		device pci 03.0 on  end # mini-hd audio
 		device pci 13.0 off end # Smart Sound Audio DSP
-		device pci 14.0 on end # USB3 XHCI
-		device pci 15.0 on end # Serial I/O DMA
-		device pci 15.1 on end # I2C0
-		device pci 15.2 on end # I2C1
+		device pci 14.0 on  end # USB3 XHCI
+		device pci 15.0 on  end # Serial I/O DMA
+		device pci 15.1 on  end # I2C0
+		device pci 15.2 on  end # I2C1
 		device pci 15.3 off end # GSPI0
 		device pci 15.4 off end # GSPI1
 		device pci 15.5 off end # UART0
 		device pci 15.6 off end # UART1
-		device pci 16.0 on end # Management Engine Interface 1
+		device pci 16.0 on  end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT
 		device pci 17.0 off end # SDIO
 		device pci 19.0 off end # GbE
-		device pci 1b.0 on end # High Definition Audio
-		device pci 1c.0 on end # PCIe Port #1
+		device pci 1b.0 on  end # High Definition Audio
+		device pci 1c.0 on  end # PCIe Port #1
 		device pci 1c.1 off end # PCIe Port #2
 		device pci 1c.2 off end # PCIe Port #3
 		device pci 1c.3 off end # PCIe Port #4
 		device pci 1c.4 off end # PCIe Port #5
 		device pci 1c.5 off end # PCIe Port #6
-		device pci 1d.0 on end # USB2 EHCI
+		device pci 1d.0 on  end # USB2 EHCI
 		device pci 1e.0 off end # PCI bridge
 		device pci 1f.0 on
 			chip drivers/pc80/tpm
@@ -96,8 +84,8 @@ chip soc/intel/broadwell
 				device pnp 0c09.0 on end
 			end
 		end # LPC bridge
-		device pci 1f.2 on end # SATA Controller
+		device pci 1f.2 on  end # SATA Controller
 		device pci 1f.3 off end # SMBus
-		device pci 1f.6 on end # Thermal
+		device pci 1f.6 on  end # Thermal
 	end
 end
diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
new file mode 100644
index 0000000000..70b1ebd552
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb
@@ -0,0 +1,16 @@
+chip soc/intel/broadwell
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
+	register "gpu_panel_power_up_delay" = "400"		# 40ms
+	register "gpu_panel_power_down_delay" = "150"		# 15ms
+	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
+
+	# DTLE DATA / EDGE values
+	register "sata_port0_gen3_dtle" = "0x5"
+	register "sata_port1_gen3_dtle" = "0x5"
+
+	device domain 0 on end
+end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
deleted file mode 100644
index db02565b27..0000000000
--- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb
+++ /dev/null
@@ -1,103 +0,0 @@
-chip soc/intel/broadwell
-
-	# Enable eDP Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Disable DisplayPort C Hotplug
-	register "gpu_dp_c_hotplug" = "0x00"
-
-	# Enable HDMI Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	# Set backlight PWM value for eDP
-	register "gpu_pch_backlight_pwm_hz" = "200"
-
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
-	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
-	register "gpu_panel_power_up_delay" = "400"		# 40ms
-	register "gpu_panel_power_down_delay" = "150"		# 15ms
-	register "gpu_panel_power_backlight_on_delay" = "2100"	# 210ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
-
-	register "pirqa_routing" = "0x8b"
-	register "pirqb_routing" = "0x8a"
-	register "pirqc_routing" = "0x8b"
-	register "pirqd_routing" = "0x8b"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# EC_SMI is GPIO34
-	register "alt_gp_smi_en" = "0x0004"
-	register "gpe0_en_1" = "0x00000000"
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
-
-	register "sata_port_map" = "0x1"
-	register "sio_acpi_mode" = "1"
-
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x7"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	# Force enable ASPM for PCIe Port1
-	register "pcie_port_force_aspm" = "0x01"
-
-	# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x013c0000"
-
-	register "s0ix_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
-		device pci 13.0 off end # Smart Sound Audio DSP
-		device pci 14.0 on end # USB3 XHCI
-		device pci 15.0 on end # Serial I/O DMA
-		device pci 15.1 on end # I2C0
-		device pci 15.2 on end # I2C1
-		device pci 15.3 off end # GSPI0
-		device pci 15.4 off end # GSPI1
-		device pci 15.5 off end # UART0
-		device pci 15.6 off end # UART1
-		device pci 16.0 on end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT
-		device pci 17.0 off end # SDIO
-		device pci 19.0 off end # GbE
-		device pci 1b.0 on end # High Definition Audio
-		device pci 1c.0 on end # PCIe Port #1
-		device pci 1c.1 off end # PCIe Port #2
-		device pci 1c.2 off end # PCIe Port #3
-		device pci 1c.3 off end # PCIe Port #4
-		device pci 1c.4 off end # PCIe Port #5
-		device pci 1c.5 off end # PCIe Port #6
-		device pci 1d.0 on end # USB2 EHCI
-		device pci 1e.0 off end # PCI bridge
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC bridge
-		device pci 1f.2 on end # SATA Controller
-		device pci 1f.3 off end # SMBus
-		device pci 1f.6 on end # Thermal
-	end
-end
diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
new file mode 100644
index 0000000000..67b9131c65
--- /dev/null
+++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
@@ -0,0 +1,16 @@
+chip soc/intel/broadwell
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
+	register "gpu_panel_power_up_delay" = "400"		# 40ms
+	register "gpu_panel_power_down_delay" = "150"		# 15ms
+	register "gpu_panel_power_backlight_on_delay" = "2100"	# 210ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
+
+	# DTLE DATA / EDGE values
+	register "sata_port0_gen3_dtle" = "0x7"
+	register "sata_port1_gen3_dtle" = "0x5"
+
+	device domain 0 on end
+end
diff --git a/src/mainboard/google/auron/variants/buddy/devicetree.cb b/src/mainboard/google/auron/variants/buddy/devicetree.cb
deleted file mode 100644
index e12882f413..0000000000
--- a/src/mainboard/google/auron/variants/buddy/devicetree.cb
+++ /dev/null
@@ -1,110 +0,0 @@
-chip soc/intel/broadwell
-
-	# Enable eDP Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Disable DisplayPort C Hotplug
-	register "gpu_dp_c_hotplug" = "0x00"
-
-	# Enable HDMI Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	# Set backlight PWM value for eDP
-	register "gpu_pch_backlight_pwm_hz" = "200"
-
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
-	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
-	register "gpu_panel_power_up_delay" = "400"		# 40ms
-	register "gpu_panel_power_down_delay" = "150"		# 15ms
-	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
-
-	register "pirqa_routing" = "0x8b"
-	register "pirqb_routing" = "0x8a"
-	register "pirqc_routing" = "0x8b"
-	register "pirqd_routing" = "0x8b"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# EC_SMI is GPIO34
-	register "alt_gp_smi_en" = "0x0004"
-	register "gpe0_en_1" = "0x00000000"
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
-
-	register "sata_port_map" = "0x1"
-	register "sata_devslp_disable" = "0x1"
-
-	register "sio_acpi_mode" = "1"
-	register "sio_i2c0_voltage" = "1" # 1.8V
-	register "sio_i2c1_voltage" = "0" # 3.3V
-
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	# Force enable ASPM for PCIe Port 5
-	register "pcie_port_force_aspm" = "0x10"
-
-	# Enable port coalescing
-	register "pcie_port_coalesce" = "1"
-
-	# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x01220000"
-
-	register "s0ix_enable" = "0"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
-		device pci 13.0 on end # Smart Sound Audio DSP
-		device pci 14.0 on end # USB3 XHCI
-		device pci 15.0 on end # Serial I/O DMA
-		device pci 15.1 on end # I2C0
-		device pci 15.2 on end # I2C1
-		device pci 15.3 off end # GSPI0
-		device pci 15.4 off end # GSPI1
-		device pci 15.5 off end # UART0
-		device pci 15.6 off end # UART1
-		device pci 16.0 on end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT
-		device pci 17.0 off end # SDIO
-		device pci 19.0 off end # GbE
-		device pci 1b.0 off end # High Definition Audio
-		device pci 1c.0 off end # PCIe Port #1
-		device pci 1c.1 off end # PCIe Port #2
-		device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
-		device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
-		device pci 1c.4 on end # PCIe Port #5
-		device pci 1c.5 off end # PCIe Port #6
-		device pci 1d.0 on end # USB2 EHCI
-		device pci 1e.0 off end # PCI bridge
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC bridge
-		device pci 1f.2 on end # SATA Controller
-		device pci 1f.3 on end # SMBus
-		device pci 1f.6 on end # Thermal
-	end
-end
diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb
new file mode 100644
index 0000000000..f814280b15
--- /dev/null
+++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb
@@ -0,0 +1,39 @@
+chip soc/intel/broadwell
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
+	register "gpu_panel_power_up_delay" = "400"		# 40ms
+	register "gpu_panel_power_down_delay" = "150"		# 15ms
+	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
+
+	register "sata_devslp_disable" = "0x1"
+
+	register "sio_i2c0_voltage" = "1" # 1.8V
+	register "sio_i2c1_voltage" = "0" # 3.3V
+
+	# DTLE DATA / EDGE values
+	register "sata_port0_gen3_dtle" = "0x5"
+	register "sata_port1_gen3_dtle" = "0x5"
+
+	# Force enable ASPM for PCIe Port 5
+	register "pcie_port_force_aspm" = "0x10"
+
+	# Enable port coalescing
+	register "pcie_port_coalesce" = "1"
+
+	# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
+	register "icc_clock_disable" = "0x01220000"
+
+	register "s0ix_enable" = "0"
+
+	device domain 0 on
+		device pci 13.0 on  end # Smart Sound Audio DSP
+		device pci 1b.0 off end # High Definition Audio
+		device pci 1c.0 off end # PCIe Port #1
+		device pci 1c.2 on  end # PCIe Port #3 - LAN (becomes RP1)
+		device pci 1c.3 on  end # PCIe Port #4 - WLAN (becomes RP2)
+		device pci 1f.3 on  end # SMBus
+	end
+end
diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb
deleted file mode 100644
index 230f5bd009..0000000000
--- a/src/mainboard/google/auron/variants/gandof/devicetree.cb
+++ /dev/null
@@ -1,103 +0,0 @@
-chip soc/intel/broadwell
-
-	# Enable eDP Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Disable DisplayPort C Hotplug
-	register "gpu_dp_c_hotplug" = "0x00"
-
-	# Enable HDMI Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	# Set backlight PWM value for eDP
-	register "gpu_pch_backlight_pwm_hz" = "200"
-
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
-	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
-	register "gpu_panel_power_up_delay" = "400"		# 40ms
-	register "gpu_panel_power_down_delay" = "150"		# 15ms
-	register "gpu_panel_power_backlight_on_delay" = "500"	# 50ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
-
-	register "pirqa_routing" = "0x8b"
-	register "pirqb_routing" = "0x8a"
-	register "pirqc_routing" = "0x8b"
-	register "pirqd_routing" = "0x8b"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# EC_SMI is GPIO34
-	register "alt_gp_smi_en" = "0x0004"
-	register "gpe0_en_1" = "0x00000000"
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
-
-	register "sata_port_map" = "0x1"
-	register "sio_acpi_mode" = "1"
-
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	# Force enable ASPM for PCIe Port1
-	register "pcie_port_force_aspm" = "0x01"
-
-	# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x013c0000"
-
-	register "s0ix_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
-		device pci 13.0 off end # Smart Sound Audio DSP
-		device pci 14.0 on end # USB3 XHCI
-		device pci 15.0 on end # Serial I/O DMA
-		device pci 15.1 on end # I2C0
-		device pci 15.2 on end # I2C1
-		device pci 15.3 off end # GSPI0
-		device pci 15.4 off end # GSPI1
-		device pci 15.5 off end # UART0
-		device pci 15.6 off end # UART1
-		device pci 16.0 on end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT
-		device pci 17.0 off end # SDIO
-		device pci 19.0 off end # GbE
-		device pci 1b.0 on end # High Definition Audio
-		device pci 1c.0 on end # PCIe Port #1
-		device pci 1c.1 off end # PCIe Port #2
-		device pci 1c.2 off end # PCIe Port #3
-		device pci 1c.3 off end # PCIe Port #4
-		device pci 1c.4 off end # PCIe Port #5
-		device pci 1c.5 off end # PCIe Port #6
-		device pci 1d.0 on end # USB2 EHCI
-		device pci 1e.0 off end # PCI bridge
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC bridge
-		device pci 1f.2 on end # SATA Controller
-		device pci 1f.3 off end # SMBus
-		device pci 1f.6 on end # Thermal
-	end
-end
diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb
new file mode 100644
index 0000000000..e35d3a5529
--- /dev/null
+++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb
@@ -0,0 +1,16 @@
+chip soc/intel/broadwell
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
+	register "gpu_panel_power_up_delay" = "400"		# 40ms
+	register "gpu_panel_power_down_delay" = "150"		# 15ms
+	register "gpu_panel_power_backlight_on_delay" = "500"	# 50ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
+
+	# DTLE DATA / EDGE values
+	register "sata_port0_gen3_dtle" = "0x5"
+	register "sata_port1_gen3_dtle" = "0x5"
+
+	device domain 0 on end
+end
diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb
deleted file mode 100644
index 1983045983..0000000000
--- a/src/mainboard/google/auron/variants/lulu/devicetree.cb
+++ /dev/null
@@ -1,104 +0,0 @@
-chip soc/intel/broadwell
-
-	# Enable eDP Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Disable DisplayPort C Hotplug
-	register "gpu_dp_c_hotplug" = "0x00"
-
-	# Enable HDMI Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	# Set backlight PWM value for eDP
-	register "gpu_pch_backlight_pwm_hz" = "200"
-
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
-	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
-	register "gpu_panel_power_up_delay" = "400"		# 40ms
-	register "gpu_panel_power_down_delay" = "150"		# 15ms
-	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
-	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
-
-	register "pirqa_routing" = "0x8b"
-	register "pirqb_routing" = "0x8a"
-	register "pirqc_routing" = "0x8b"
-	register "pirqd_routing" = "0x8b"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# EC_SMI is GPIO34
-	register "alt_gp_smi_en" = "0x0004"
-	register "gpe0_en_1" = "0x00000000"
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
-
-	register "sata_port_map" = "0x1"
-
-	register "sio_acpi_mode" = "1"
-
-	# DTLE DATA / EDGE values
-	register "sata_port0_gen3_dtle" = "0x5"
-	register "sata_port1_gen3_dtle" = "0x5"
-
-	# Force enable ASPM for PCIe Port1
-	register "pcie_port_force_aspm" = "0x01"
-
-	# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x013c0000"
-
-	register "s0ix_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 02.0 on end # vga controller
-		device pci 03.0 on end # mini-hd audio
-		device pci 13.0 off end # Smart Sound Audio DSP
-		device pci 14.0 on end # USB3 XHCI
-		device pci 15.0 on end # Serial I/O DMA
-		device pci 15.1 on end # I2C0
-		device pci 15.2 on end # I2C1
-		device pci 15.3 off end # GSPI0
-		device pci 15.4 off end # GSPI1
-		device pci 15.5 off end # UART0
-		device pci 15.6 off end # UART1
-		device pci 16.0 on end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT
-		device pci 17.0 off end # SDIO
-		device pci 19.0 off end # GbE
-		device pci 1b.0 on end # High Definition Audio
-		device pci 1c.0 on end # PCIe Port #1
-		device pci 1c.1 off end # PCIe Port #2
-		device pci 1c.2 off end # PCIe Port #3
-		device pci 1c.3 off end # PCIe Port #4
-		device pci 1c.4 off end # PCIe Port #5
-		device pci 1c.5 off end # PCIe Port #6
-		device pci 1d.0 on end # USB2 EHCI
-		device pci 1e.0 off end # PCI bridge
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC bridge
-		device pci 1f.2 on end # SATA Controller
-		device pci 1f.3 off end # SMBus
-		device pci 1f.6 on end # Thermal
-	end
-end
diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb
new file mode 100644
index 0000000000..70b1ebd552
--- /dev/null
+++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb
@@ -0,0 +1,16 @@
+chip soc/intel/broadwell
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "5"		# 400ms
+	register "gpu_panel_power_up_delay" = "400"		# 40ms
+	register "gpu_panel_power_down_delay" = "150"		# 15ms
+	register "gpu_panel_power_backlight_on_delay" = "70"	# 7ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
+
+	# DTLE DATA / EDGE values
+	register "sata_port0_gen3_dtle" = "0x5"
+	register "sata_port1_gen3_dtle" = "0x5"
+
+	device domain 0 on end
+end
diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb
deleted file mode 100644
index 434ecc80b9..0000000000
--- a/src/mainboard/google/auron/variants/samus/devicetree.cb
+++ /dev/null
@@ -1,107 +0,0 @@
-chip soc/intel/broadwell
-
-	# Enable eDP Hotplug with 6ms pulse
-	register "gpu_dp_d_hotplug" = "0x06"
-
-	# Enable DDI1 Hotplug with 6ms pulse
-	register "gpu_dp_b_hotplug" = "0x06"
-
-	# Enable DDI2 Hotplug with 6ms pulse
-	register "gpu_dp_c_hotplug" = "0x06"
-
-	# Set backlight PWM value for eDP
-	register "gpu_pch_backlight_pwm_hz" = "200"
-
-	# Enable Panel and configure power delays
-	register "gpu_panel_port_select" = "1"			# eDP
-	register "gpu_panel_power_cycle_delay" = "6"		# 500ms
-	register "gpu_panel_power_up_delay" = "2000"		# 200ms
-	register "gpu_panel_power_down_delay" = "500"		# 50ms
-	register "gpu_panel_power_backlight_on_delay" = "2000"	# 200ms
-	register "gpu_panel_power_backlight_off_delay" = "2000"	# 200ms
-
-	register "pirqa_routing" = "0x8b"
-	register "pirqb_routing" = "0x8a"
-	register "pirqc_routing" = "0x8b"
-	register "pirqd_routing" = "0x8b"
-	register "pirqe_routing" = "0x80"
-	register "pirqf_routing" = "0x80"
-	register "pirqg_routing" = "0x80"
-	register "pirqh_routing" = "0x80"
-
-	# EC range is 0x800-0x9ff
-	register "gen1_dec" = "0x00fc0801"
-	register "gen2_dec" = "0x00fc0901"
-
-	# EC_SMI is GPIO34
-	register "alt_gp_smi_en" = "0x0004"
-	register "gpe0_en_1" = "0x00000000"
-	# EC_SCI is GPIO36
-	register "gpe0_en_2" = "0x00000010"
-	register "gpe0_en_3" = "0x00000000"
-	register "gpe0_en_4" = "0x00000000"
-
-	register "sata_port_map" = "0x1"
-	register "sata_port0_gen3_tx" = "0x72"
-	register "sio_acpi_mode" = "1"
-
-	# Set I2C0 to 1.8V
-	register "sio_i2c0_voltage" = "1"
-
-	# Force enable ASPM for PCIe Port 3
-	register "pcie_port_force_aspm" = "0x04"
-	register "pcie_port_coalesce" = "1"
-
-	# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
-	register "icc_clock_disable" = "0x013b0000"
-
-	# Disable S0ix for now
-	register "s0ix_enable" = "0"
-
-	register "vr_slow_ramp_rate_set" = "3"
-	register "vr_slow_ramp_rate_enable" = "1"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-	device domain 0 on
-		device pci 00.0 on  end # host bridge
-		device pci 02.0 on  end # vga controller
-		device pci 03.0 on  end # mini-hd audio
-		device pci 13.0 on  end # Smart Sound Audio DSP
-		device pci 14.0 on  end # USB3 XHCI
-		device pci 15.0 on  end # Serial I/O DMA
-		device pci 15.1 on  end # I2C0
-		device pci 15.2 on  end # I2C1
-		device pci 15.3 on  end # GSPI0
-		device pci 15.4 off end # GSPI1
-		device pci 15.5 off end # UART0
-		device pci 15.6 off end # UART1
-		device pci 16.0 on  end # Management Engine Interface 1
-		device pci 16.1 off end # Management Engine Interface 2
-		device pci 16.2 off end # Management Engine IDE-R
-		device pci 16.3 off end # Management Engine KT
-		device pci 17.0 off end # SDIO
-		device pci 19.0 off end # GbE
-		device pci 1b.0 off end # High Definition Audio
-		device pci 1c.0 off end # PCIe Port #1
-		device pci 1c.1 off end # PCIe Port #2
-		device pci 1c.2 on  end # PCIe Port #3
-		device pci 1c.3 off end # PCIe Port #4
-		device pci 1c.4 off end # PCIe Port #5
-		device pci 1c.5 off end # PCIe Port #6
-		device pci 1d.0 off end # USB2 EHCI
-		device pci 1e.0 off end # PCI bridge
-		device pci 1f.0 on
-			chip drivers/pc80/tpm
-				device pnp 0c31.0 on end
-			end
-			chip ec/google/chromeec
-				device pnp 0c09.0 on end
-			end
-		end # LPC bridge
-		device pci 1f.2 on  end # SATA Controller
-		device pci 1f.3 off end # SMBus
-		device pci 1f.6 on  end # Thermal
-	end
-end
diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb
new file mode 100644
index 0000000000..93e96cac3f
--- /dev/null
+++ b/src/mainboard/google/auron/variants/samus/overridetree.cb
@@ -0,0 +1,40 @@
+chip soc/intel/broadwell
+
+	# Enable DDI2 Hotplug with 6ms pulse
+	register "gpu_dp_c_hotplug" = "0x06"
+
+	# Enable Panel and configure power delays
+	register "gpu_panel_port_select" = "1"			# eDP
+	register "gpu_panel_power_cycle_delay" = "6"		# 500ms
+	register "gpu_panel_power_up_delay" = "2000"		# 200ms
+	register "gpu_panel_power_down_delay" = "500"		# 50ms
+	register "gpu_panel_power_backlight_on_delay" = "2000"	# 200ms
+	register "gpu_panel_power_backlight_off_delay" = "2000"	# 200ms
+
+	register "sata_port0_gen3_tx" = "0x72"
+
+	# Set I2C0 to 1.8V
+	register "sio_i2c0_voltage" = "1"
+
+	# Force enable ASPM for PCIe Port 3
+	register "pcie_port_force_aspm" = "0x04"
+	register "pcie_port_coalesce" = "1"
+
+	# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
+	register "icc_clock_disable" = "0x013b0000"
+
+	# Disable S0ix for now
+	register "s0ix_enable" = "0"
+
+	register "vr_slow_ramp_rate_set" = "3"
+	register "vr_slow_ramp_rate_enable" = "1"
+
+	device domain 0 on
+		device pci 13.0 on  end # Smart Sound Audio DSP
+		device pci 15.3 on  end # GSPI0
+		device pci 1b.0 off end # High Definition Audio
+		device pci 1c.0 off end # PCIe Port #1
+		device pci 1c.2 on  end # PCIe Port #3
+		device pci 1d.0 off end # USB2 EHCI
+	end
+end