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authorYouness Alaoui <youness.alaoui@puri.sm>2017-05-08 15:22:03 -0400
committerMartin Roth <martinroth@google.com>2017-06-09 16:59:41 +0200
commitb191c9f0ab5e9c4fb3f355a0cc2674e7861b0a68 (patch)
tree31a25616d101ee438bd5df25a41313c8432745c9
parentbb5fb64e11aa7eb6534a5dd5a06d5ea29dc4d411 (diff)
downloadcoreboot-b191c9f0ab5e9c4fb3f355a0cc2674e7861b0a68.tar.xz
soc/broadwell: Allow disabling of PCIe ASPM options
The ASPM options (L1 substates, CLKREQ support, Common Clock and ASPM) are hardcoded for broadwell chips, but some boards may not support these ASPM options even if the SoC does support it (non-wired CLKREQ pin for example). This is required to disable L1 substates on the Purism/Librem 13 which seems to have issues with NVMe drives falling into L1.2 state and not being able to exit that state. Change-Id: I2c7173af1d482cccdc784e3fa44ecbb5d38ddc34 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
-rw-r--r--src/soc/intel/broadwell/Kconfig20
1 files changed, 16 insertions, 4 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 34f515f145..51322012d0 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -27,10 +27,6 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE
select REG_SCRIPT
select PARALLEL_MP
- select PCIEXP_ASPM
- select PCIEXP_COMMON_CLOCK
- select PCIEXP_CLK_PM
- select PCIEXP_L1_SUB_STATE
select RTC
select SMM_TSEG
select SMP
@@ -46,6 +42,22 @@ config CPU_SPECIFIC_OPTIONS
select HAVE_SPI_CONSOLE_SUPPORT
select CPU_INTEL_COMMON
+config PCIEXP_ASPM
+ bool
+ default y
+
+config PCIEXP_COMMON_CLOCK
+ bool
+ default y
+
+config PCIEXP_CLK_PM
+ bool
+ default y
+
+config PCIEXP_L1_SUB_STATE
+ bool
+ default y
+
config VBOOT
select VBOOT_STARTS_IN_ROMSTAGE