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authorAngel Pons <th3fanbus@gmail.com>2020-06-22 17:41:49 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-01 18:14:31 +0000
commitb6397070561fdbe13ae4a5e5f6b9766426800d55 (patch)
tree0942f652cd7fe3fae9494598d093ba2c71058e3b
parent8edfddcb54cf28a9c5deb4d97d131a47e77cda07 (diff)
downloadcoreboot-b6397070561fdbe13ae4a5e5f6b9766426800d55.tar.xz
nb/intel/ironlake: Drop copy-pasted and dead code
This function was copy-pasted, comments included, from Sandy Bridge. However, it is only called with 0x0044 as the northbridge's PCI ID. Therefore, `bridge_silicon_revision() & BASE_REV_MASK` will always evaluate to 0x40, which never equals `BASE_REV_SNB`, that is, 0x00. As the condition is always false, treat this code as dead and drop it. Following a similar reasoning, all direct comparisons against SNB steppings will always be true, because `bridge_silicon_revision()` returns at least 0x40 which is always larger than either `SNB_STEP_D0` or `SNB_STEP_D1`. So, drop all but the code path that is actually used. Change-Id: I5219a6af3df98ed77c9c4abfb9a63c2ebf8171bb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42697 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
-rw-r--r--src/northbridge/intel/ironlake/northbridge.c32
1 files changed, 3 insertions, 29 deletions
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c
index f53b03ea8b..415c142946 100644
--- a/src/northbridge/intel/ironlake/northbridge.c
+++ b/src/northbridge/intel/ironlake/northbridge.c
@@ -161,39 +161,13 @@ static void northbridge_dmi_init(struct device *dev)
DMIBAR32(0x1c4) = 0xffffffff;
DMIBAR32(0x1d0) = 0xffffffff;
- /* Steps prior to DMI ASPM */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
- reg32 = DMIBAR32(0x250);
- reg32 &= ~((1 << 22) | (1 << 20));
- reg32 |= (1 << 21);
- DMIBAR32(0x250) = reg32;
- }
-
reg32 = DMIBAR32(0x238);
reg32 |= (1 << 29);
DMIBAR32(0x238) = reg32;
- if (bridge_silicon_revision() >= SNB_STEP_D0) {
- reg32 = DMIBAR32(0x1f8);
- reg32 |= (1 << 16);
- DMIBAR32(0x1f8) = reg32;
- } else if (bridge_silicon_revision() >= SNB_STEP_D1) {
- reg32 = DMIBAR32(0x1f8);
- reg32 &= ~(1 << 26);
- reg32 |= (1 << 16);
- DMIBAR32(0x1f8) = reg32;
-
- reg32 = DMIBAR32(0x1fc);
- reg32 |= (1 << 12) | (1 << 23);
- DMIBAR32(0x1fc) = reg32;
- }
-
- /* Enable ASPM on SNB link, should happen before PCH link */
- if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
- reg32 = DMIBAR32(0xd04);
- reg32 |= (1 << 4);
- DMIBAR32(0xd04) = reg32;
- }
+ reg32 = DMIBAR32(0x1f8);
+ reg32 |= (1 << 16);
+ DMIBAR32(0x1f8) = reg32;
reg32 = DMIBAR32(0x88);
reg32 |= (1 << 1) | (1 << 0);