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authorFurquan Shaikh <furquan@google.com>2019-07-09 14:22:46 -0700
committerFurquan Shaikh <furquan@google.com>2019-07-11 06:01:15 +0000
commitb8501c7c5f00a664ff644324af363d43c5af1bc2 (patch)
tree5c6c4317049c9bfaf2bd15b433245665a24c5b53
parent10a9432cc2ad77234442bd639194c5a80050854e (diff)
downloadcoreboot-b8501c7c5f00a664ff644324af363d43c5af1bc2.tar.xz
mb/google/hatch: Fix interrupt trigger type for GPP_H0(HP_INT_L)
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since it needs to trigger on both edges. With GPIO IRQ, it is necessary to configure the trigger type in coreboot to match the ACPI configuration. This is because: 1. ACPI configuration is used by intel-pinctrl driver in Linux kernel to re-configure the trigger type for the pad in GPIO DW0 config register. This is done when kernel driver probes and requests irq for its device. 2. On resume from S3, the pad configuration gets reset and coreboot sets the trigger type to LEVEL. However, kernel driver does not probe again. This results in the trigger type being configured incorrectly. This change updates the GPIO configuration for GPP_H0 to set the same trigger type as advertised in ACPI for the kernel. BUG=b:132672011 TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0 works fine on boot as well as after suspend/resume. Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/mainboard/google/hatch/variants/baseboard/gpio.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index 1da3d756e2..a466972048 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -329,7 +329,7 @@ static const struct pad_config gpio_table[] = {
/*
* H0 : HP_INT_L
*/
- PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, LEVEL),
+ PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH),
/* H1 : CNV_RF_RESET_L */
PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
/* H2 : CNV_CLKREQ0 */