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authorUwe Hermann <uwe@hermann-uwe.de>2010-12-16 19:57:54 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-12-16 19:57:54 +0000
commitb9c224e9c53c8e0df9835c0cfe5d28f98678c375 (patch)
tree577f19883dbe287194bc12cbf00c954f990ccf84
parentc36d506a05ad02f65d92d0f5a7b70a7c25666445 (diff)
downloadcoreboot-b9c224e9c53c8e0df9835c0cfe5d28f98678c375.tar.xz
Add TINY_BOOTBLOCK support for the SiS966 southbridge.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/mainboard/gigabyte/ga_2761gxdk/romstage.c2
-rw-r--r--src/southbridge/sis/sis966/Kconfig5
-rw-r--r--src/southbridge/sis/sis966/bootblock.c (renamed from src/southbridge/sis/sis966/enable_rom.c)22
-rw-r--r--src/southbridge/sis/sis966/enable_usbdebug.c6
-rw-r--r--src/southbridge/sis/sis966/ide.c1
-rw-r--r--src/southbridge/sis/sis966/sis966.h13
6 files changed, 31 insertions, 18 deletions
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 50c52b67c5..da6eb7701e 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -40,7 +40,6 @@
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/sis/sis966/sis966.h"
#include "southbridge/sis/sis966/early_smbus.c"
-#include "southbridge/sis/sis966/enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
@@ -131,7 +130,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Allow the HT devices to be found */
enumerate_ht_chain();
sio_setup();
- sis966_enable_rom();
}
if (bist == 0)
diff --git a/src/southbridge/sis/sis966/Kconfig b/src/southbridge/sis/sis966/Kconfig
index bbb5ee971b..867d08c347 100644
--- a/src/southbridge/sis/sis966/Kconfig
+++ b/src/southbridge/sis/sis966/Kconfig
@@ -2,6 +2,11 @@ config SOUTHBRIDGE_SIS_SIS966
bool
select IOAPIC
select HAVE_USBDEBUG
+ select TINY_BOOTBLOCK
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+ string
+ default "southbridge/sis/sis966/bootblock.c" if SOUTHBRIDGE_SIS_SIS966
config ID_SECTION_OFFSET
hex
diff --git a/src/southbridge/sis/sis966/enable_rom.c b/src/southbridge/sis/sis966/bootblock.c
index 63ef616563..1ff3cda2b4 100644
--- a/src/southbridge/sis/sis966/enable_rom.c
+++ b/src/southbridge/sis/sis966/bootblock.c
@@ -23,19 +23,25 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
- #define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_ids.h>
+#include "sis966.h"
static void sis966_enable_rom(void)
{
device_t addr;
- /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
- addr = pci_locate_device(PCI_ID(0x1039, 0x0966), 0);
+ /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */
+ addr = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS,
+ PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
- /* Set the 4MB enable bit bit */
+ /* Set the 4MB enable bit(s). */
pci_write_config8(addr, 0x40, pci_read_config8(addr, 0x40) | 0x11);
}
+
+static void bootblock_southbridge_init(void)
+{
+ sis966_enable_rom();
+}
diff --git a/src/southbridge/sis/sis966/enable_usbdebug.c b/src/southbridge/sis/sis966/enable_usbdebug.c
index a82e941b3a..fb20c960f3 100644
--- a/src/southbridge/sis/sis966/enable_usbdebug.c
+++ b/src/southbridge/sis/sis966/enable_usbdebug.c
@@ -30,12 +30,6 @@
#include <device/pci_def.h>
#include "sis966.h"
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
-#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
-#else
-#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
-#endif
-
void set_debug_port(unsigned int port)
{
u32 dword;
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index c57be5ade7..90ea002a5a 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -30,6 +30,7 @@
#include <device/pci_ops.h>
#include <arch/io.h>
#include "sis966.h"
+#include "chip.h"
uint8_t SiS_SiS5513_init[49][3]={
{0x04, 0xFF, 0x05},
diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index 324beef3c9..a451bf7e55 100644
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -22,6 +22,12 @@
#ifndef SIS966_H
#define SIS966_H
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
+#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE
+#else
+#define SIS966_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE
+#endif
+
#define DEBUG_AZA 0
#define DEBUG_NIC 0
#define DEBUG_IDE 0
@@ -29,9 +35,12 @@
#define DEBUG_USB 0
#define DEBUG_USB2 0
-#include "chip.h"
-
+#if !defined(__ROMCC__)
void sis966_enable(device_t dev);
+#endif
+
+#if defined(__PRE_RAM__) && !defined(__ROMCC__)
void sis966_enable_usbdebug(unsigned int port);
+#endif
#endif /* SIS966_H */