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authorRaul E Rangel <rrangel@chromium.org>2020-06-04 16:36:33 -0600
committerPatrick Georgi <pgeorgi@google.com>2020-06-06 09:41:44 +0000
commitbe2b5ac0eac915cc37e2cc366725e9fdf634ef12 (patch)
tree766591f9af6a6dcc651272cf52f78965fa4da9bd
parentf9b9166431d758a6bed27008fc49f752b499f83d (diff)
downloadcoreboot-be2b5ac0eac915cc37e2cc366725e9fdf634ef12.tar.xz
soc/amd/picasso: Use MSR_CSTATE_ADDRESS
This is a standard MSR. No reason for picasso to define its own. BUG=b:147042464 TEST=Boot to OS on trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/amd/picasso/include/soc/cpu.h2
-rw-r--r--src/soc/amd/picasso/southbridge.c3
2 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/amd/picasso/include/soc/cpu.h b/src/soc/amd/picasso/include/soc/cpu.h
index 99b31c3bfe..fd9c5fee48 100644
--- a/src/soc/amd/picasso/include/soc/cpu.h
+++ b/src/soc/amd/picasso/include/soc/cpu.h
@@ -3,8 +3,6 @@
#ifndef __PICASSO_CPU_H__
#define __PICASSO_CPU_H__
-#define CSTATE_BASE_REG 0xc0010073
-
int get_cpu_count(void);
void check_mca(void);
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 123eca772a..a18f5a37bd 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -3,6 +3,7 @@
#include <console/console.h>
#include <device/mmio.h>
#include <bootstate.h>
+#include <cpu/amd/msr.h>
#include <cpu/x86/smm.h>
#include <cpu/x86/msr.h>
#include <device/device.h>
@@ -318,7 +319,7 @@ static void sb_init_acpi_ports(void)
/* CpuControl is in \_SB.CP00, 6 bytes */
cst_addr.hi = 0;
cst_addr.lo = ACPI_CPU_CONTROL;
- wrmsr(CSTATE_BASE_REG, cst_addr);
+ wrmsr(MSR_CSTATE_ADDRESS, cst_addr);
if (CONFIG(HAVE_SMI_HANDLER)) {
/* APMC - SMI Command Port */