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authorAngel Pons <th3fanbus@gmail.com>2020-01-01 18:54:31 +0100
committerNico Huber <nico.h@gmx.de>2020-01-10 10:16:02 +0000
commitc045a02174b31c1ce614cb04b88b94003d842973 (patch)
tree3be6278ff3cde82cb7becacf1e9fa65e680c3957
parentb6df6b065cffea9b93f6fdbd041ee15e4ec6fd61 (diff)
downloadcoreboot-c045a02174b31c1ce614cb04b88b94003d842973.tar.xz
mb/google/nyan/devicetree.cb: Correct some comments
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few minor typos. Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
-rw-r--r--src/mainboard/google/nyan/devicetree.cb10
-rw-r--r--src/mainboard/google/nyan_big/devicetree.cb10
-rw-r--r--src/mainboard/google/nyan_blaze/devicetree.cb10
3 files changed, 15 insertions, 15 deletions
diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb
index 5db8192ac9..ae4f5bc1f7 100644
--- a/src/mainboard/google/nyan/devicetree.cb
+++ b/src/mainboard/google/nyan/devicetree.cb
@@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
-# N.B. We ae not using the device tree in an effective way.
-# We need to change this in future such that the on-soc
+# N.B. We are not using the device tree in an effective way.
+# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
-# in parallel. This is even easier on the ARM SOCs since there
+# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
-# cf8/cfc registers found on PCs.
+# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@@ -39,7 +39,7 @@ chip soc/nvidia/tegra124
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
- # various panel delay time
+ # Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
diff --git a/src/mainboard/google/nyan_big/devicetree.cb b/src/mainboard/google/nyan_big/devicetree.cb
index 5db8192ac9..ae4f5bc1f7 100644
--- a/src/mainboard/google/nyan_big/devicetree.cb
+++ b/src/mainboard/google/nyan_big/devicetree.cb
@@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
-# N.B. We ae not using the device tree in an effective way.
-# We need to change this in future such that the on-soc
+# N.B. We are not using the device tree in an effective way.
+# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
-# in parallel. This is even easier on the ARM SOCs since there
+# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
-# cf8/cfc registers found on PCs.
+# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@@ -39,7 +39,7 @@ chip soc/nvidia/tegra124
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
- # various panel delay time
+ # Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"
diff --git a/src/mainboard/google/nyan_blaze/devicetree.cb b/src/mainboard/google/nyan_blaze/devicetree.cb
index 5db8192ac9..ae4f5bc1f7 100644
--- a/src/mainboard/google/nyan_blaze/devicetree.cb
+++ b/src/mainboard/google/nyan_blaze/devicetree.cb
@@ -15,12 +15,12 @@
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
-# N.B. We ae not using the device tree in an effective way.
-# We need to change this in future such that the on-soc
+# N.B. We are not using the device tree in an effective way.
+# We need to change this in future such that the on-SoC
# devices are 'chips', which will allow us to go at them
-# in parallel. This is even easier on the ARM SOCs since there
+# in parallel. This is even easier on the ARM SoCs since there
# are no single-access resources such as the infamous
-# cf8/cfc registers found on PCs.
+# 0xcf8/0xcfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
@@ -39,7 +39,7 @@ chip soc/nvidia/tegra124
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
- # various panel delay time
+ # Various panel delay times
register "vdd_delay_ms" = "200"
register "pwm_to_bl_delay_ms" = "10"
register "vdd_to_hpd_delay_ms" = "200"