Add the support for RDC R8610 Northbridge

So far the it just setups the internal resource management for coreboot and
detects the memory size.

Change-Id: I8506390fa6656abfa40d92b8f6ede9b91fe98680
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/807
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 files changed, 187 insertions, 0 deletions

diff --git a/src/northbridge/Kconfig b/src/northbridge/Kconfig
index eeedc894fa..b2b8abed6b 100644
--- a/src/northbridge/Kconfig
+++ b/src/northbridge/Kconfig
@@ -1,3 +1,4 @@
 source src/northbridge/amd/Kconfig
 source src/northbridge/intel/Kconfig
+source src/northbridge/rdc/Kconfig
 source src/northbridge/via/Kconfig
diff --git a/src/northbridge/Makefile.inc b/src/northbridge/Makefile.inc
index 57273cf8c3..283ba4ecbe 100644
--- a/src/northbridge/Makefile.inc
+++ b/src/northbridge/Makefile.inc
@@ -1,3 +1,4 @@
 subdirs-y += amd
 subdirs-y += intel
+subdirs-y += rdc
 subdirs-y += via
diff --git a/src/northbridge/rdc/Kconfig b/src/northbridge/rdc/Kconfig
new file mode 100644
index 0000000000..73ac740abd
--- /dev/null
+++ b/src/northbridge/rdc/Kconfig
@@ -0,0 +1 @@
+source src/northbridge/rdc/r8610/Kconfig
diff --git a/src/northbridge/rdc/Makefile.inc b/src/northbridge/rdc/Makefile.inc
new file mode 100644
index 0000000000..766fea21b4
--- /dev/null
+++ b/src/northbridge/rdc/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-$(CONFIG_NORTHBRIDGE_RDC_R8610) += r8610
+
diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig
new file mode 100644
index 0000000000..85461b7f31
--- /dev/null
+++ b/src/northbridge/rdc/r8610/Kconfig
@@ -0,0 +1,2 @@
+config NORTHBRIDGE_RDC_R8610
+	bool
diff --git a/src/northbridge/rdc/r8610/Makefile.inc b/src/northbridge/rdc/r8610/Makefile.inc
new file mode 100644
index 0000000000..c97696738b
--- /dev/null
+++ b/src/northbridge/rdc/r8610/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+driver-y += northbridge.c
diff --git a/src/northbridge/rdc/r8610/chip.h b/src/northbridge/rdc/r8610/chip.h
new file mode 100644
index 0000000000..01c835697f
--- /dev/null
+++ b/src/northbridge/rdc/r8610/chip.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Corey Osgood <corey.osgood@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+struct northbridge_rdc_r8610_config {
+};
+
+extern struct chip_operations northbridge_rdc_r8610_ops;
diff --git a/src/northbridge/rdc/r8610/northbridge.c b/src/northbridge/rdc/r8610/northbridge.c
new file mode 100644
index 0000000000..48d830cddf
--- /dev/null
+++ b/src/northbridge/rdc/r8610/northbridge.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Rudolf Marek <r.marek@assembler.cz>
+ *
+ * Based on qemu-x86/northbridge.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <smbios.h>
+#include "chip.h"
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static unsigned long get_memory_size(void)
+{
+	device_t nb_dev;
+	u8 size;
+
+	nb_dev = dev_find_device(PCI_VENDOR_ID_RDC,
+				 PCI_DEVICE_ID_RDC_R8610_NB, 0);
+	size = pci_read_config8(nb_dev, 0x6d) & 0xf;
+	return (2 * 1024) << size;
+}
+
+static void cpu_pci_domain_set_resources(device_t dev)
+{
+	u32 pci_tolm = find_pci_tolm(dev->link_list);
+	unsigned long tomk = 0, tolmk;
+	int idx;
+
+	tomk = get_memory_size();
+	printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
+	       tomk, tomk / 1024);
+
+	/* Compute the top of Low memory */
+	tolmk = pci_tolm >> 10;
+	if (tolmk >= tomk) {
+		/* The PCI hole does not overlap the memory. */
+		tolmk = tomk;
+	}
+
+	/* Report the memory regions. */
+	idx = 10;
+	ram_resource(dev, idx++, 0, 640);
+	ram_resource(dev, idx++, 768, tolmk - 768);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+#endif
+
+	assign_resources(dev->link_list);
+}
+
+static void cpu_pci_domain_read_resources(struct device *dev)
+{
+	pci_domain_read_resources(dev);
+}
+
+#if CONFIG_GENERATE_SMBIOS_TABLES
+static int rdc_get_smbios_data16(int handle, unsigned long *current)
+{
+	struct smbios_type16 *t = (struct smbios_type16 *)*current;
+	int len = sizeof(struct smbios_type16);
+
+	memset(t, 0, sizeof(struct smbios_type16));
+	t->type = SMBIOS_PHYS_MEMORY_ARRAY;
+	t->handle = handle;
+	t->length = len - 2;
+	t->location = 3; /* Location: System Board */
+	t->use = 3; /* System memory */
+	t->memory_error_correction = 3; /* No error correction */
+	t->maximum_capacity = get_memory_size();
+	*current += len;
+	return len;
+}
+
+static int rdc_get_smbios_data(device_t dev, int *handle, unsigned long *current)
+{
+	int len;
+	len = rdc_get_smbios_data16(*handle, current);
+	*handle += 1;
+	return len;
+}
+#endif
+static struct device_operations pci_domain_ops = {
+	.read_resources		= cpu_pci_domain_read_resources,
+	.set_resources		= cpu_pci_domain_set_resources,
+	.enable_resources	= NULL,
+	.init			= NULL,
+	.scan_bus		= pci_domain_scan_bus,
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	.get_smbios_data	= rdc_get_smbios_data,
+#endif
+};
+
+static void enable_dev(struct device *dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+		pci_set_method(dev);
+	}
+}
+
+struct chip_operations northbridge_rdc_r8610_ops = {
+	CHIP_NAME("RDC R8610 Northbridge")
+	.enable_dev = enable_dev,
+};