diff options
| author | Shelley Chen <shchen@google.com> | 2019-03-20 13:48:00 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-22 12:23:18 +0000 |
| commit | c325fa1312ed2cbbfcb7ba6cb395146120701e7e (patch) | |
| tree | 6e9ee5fb938344a5cd74b70d690c1b8fbeb825ba | |
| parent | 5eeee58ca27bca622a142b804f15f908985a5918 (diff) | |
| download | coreboot-c325fa1312ed2cbbfcb7ba6cb395146120701e7e.tar.xz | |
mb/google/hatch: Add overridetree to hatch variant
Add serialio settings to hatch. Only applies to CML.
BUG=b:128347800
BRANCH=None
TEST=abuild
Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32003
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/google/hatch/Kconfig | 4 | ||||
| -rw-r--r-- | src/mainboard/google/hatch/variants/hatch/overridetree.cb | 18 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index f632a02d03..19c71841b2 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -80,6 +80,10 @@ config MAX_CPUS int default 8 +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH_WHL + config TPM_TIS_ACPI_INTERRUPT int default 53 # GPE0_DW1_21 (GPP_C21) diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb new file mode 100644 index 0000000000..6e6414e8a8 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + +end |