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authorNico Huber <nico.h@gmx.de>2018-10-06 18:41:44 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:34:33 +0000
commitc6fe265f68c65053f908248128347f4b860afc4e (patch)
tree8c1bcf6d399bd2fbfcb2d0077ebf7747aa65950b
parent496fb23c5df50b266aa7f20984769357ea662a20 (diff)
downloadcoreboot-c6fe265f68c65053f908248128347f4b860afc4e.tar.xz
soc/imgtech/pistachio: Convert to `board_reset()`
Change-Id: If8fc29c46e2cbc69f94ea8b6dc414a93d82ffb28 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/29050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
-rw-r--r--src/soc/imgtec/pistachio/Kconfig1
-rw-r--r--src/soc/imgtec/pistachio/reset.c2
2 files changed, 1 insertions, 2 deletions
diff --git a/src/soc/imgtec/pistachio/Kconfig b/src/soc/imgtec/pistachio/Kconfig
index 1ce488c35b..333216d15d 100644
--- a/src/soc/imgtec/pistachio/Kconfig
+++ b/src/soc/imgtec/pistachio/Kconfig
@@ -23,7 +23,6 @@ config CPU_IMGTEC_PISTACHIO
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select GENERIC_GPIO_LIB
- select HAVE_HARD_RESET
select UART_OVERRIDE_REFCLK
bool
diff --git a/src/soc/imgtec/pistachio/reset.c b/src/soc/imgtec/pistachio/reset.c
index c0e9105abf..d5d0a8188d 100644
--- a/src/soc/imgtec/pistachio/reset.c
+++ b/src/soc/imgtec/pistachio/reset.c
@@ -20,7 +20,7 @@
#define PISTACHIO_WD_ADDR 0xB8102100
#define PISTACHIO_WD_SW_RST_OFFSET 0x0000
-void do_hard_reset(void)
+void do_board_reset(void)
{
/* Generate system reset */
write32(PISTACHIO_WD_ADDR + PISTACHIO_WD_SW_RST_OFFSET, 0x1);