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authorStefan Reinauer <stepan@coresystems.de>2010-05-26 12:53:43 +0000
committerStefan Reinauer <stepan@openbios.org>2010-05-26 12:53:43 +0000
commitc8f8a6cb91e6aa5d6785f8ad09aae40048980efd (patch)
tree4f84adb80e75cc8783bc4d59c5fbb367df647a90
parent2305f748953867ddfdc0f449401148e97e78e506 (diff)
downloadcoreboot-c8f8a6cb91e6aa5d6785f8ad09aae40048980efd.tar.xz
cosmetical changes on intel's microcode.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5590 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/cpu/intel/microcode/microcode.c29
1 files changed, 14 insertions, 15 deletions
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index 93d2a687fb..9a80077a85 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -8,27 +8,26 @@
#include <cpu/intel/microcode.h>
struct microcode {
- uint32_t hdrver;
- uint32_t rev;
- uint32_t date;
- uint32_t sig;
+ u32 hdrver; /* Header Version */
+ u32 rev; /* Patch ID */
+ u32 date; /* DATE */
+ u32 sig; /* CPUID */
- uint32_t cksum;
- uint32_t ldrver;
- uint32_t pf;
+ u32 cksum; /* Checksum */
+ u32 ldrver; /* Loader Version */
+ u32 pf; /* Platform ID */
- uint32_t data_size;
- uint32_t total_size;
+ u32 data_size; /* Data size */
+ u32 total_size; /* Total size */
- uint32_t reserved[3];
- uint32_t bits[1012];
+ u32 reserved[3];
+ u32 bits[1012];
};
-
-static inline uint32_t read_microcode_rev(void)
+static inline u32 read_microcode_rev(void)
{
/* Some Intel Cpus can be very finicky about the
- * cpuid sequence used. So this is implemented in
+ * CPUID sequence used. So this is implemented in
* assembly so that it works reliably.
*/
msr_t msr;
@@ -47,7 +46,7 @@ static inline uint32_t read_microcode_rev(void)
: /* inputs */
: /* trashed */
"ecx"
- );
+ );
return msr.hi;
}