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authorAngel Pons <th3fanbus@gmail.com>2020-08-03 18:57:34 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-08-04 21:36:00 +0000
commitce3e6380b98c8e40292efa44bf6752cf34ee9af4 (patch)
tree63c583960838cd4a0f1108b5f633df3d06b6a372
parent4a2f08c846bd835808a23d1cb699899aaf31cf94 (diff)
downloadcoreboot-ce3e6380b98c8e40292efa44bf6752cf34ee9af4.tar.xz
nb/intel/ironlake/acpi.c: Factor out PCIEXBAR decoding
Other northbridges have a `decode_pcie_bar` function. Since it's not needed anywhere else, keep it as a static function for now. Change-Id: Ide42ffcebb73c3e683e0ccaf0ab3aeae805d1123 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
-rw-r--r--src/northbridge/intel/ironlake/acpi.c56
1 files changed, 28 insertions, 28 deletions
diff --git a/src/northbridge/intel/ironlake/acpi.c b/src/northbridge/intel/ironlake/acpi.c
index c954086afb..688dd5fd81 100644
--- a/src/northbridge/intel/ironlake/acpi.c
+++ b/src/northbridge/intel/ironlake/acpi.c
@@ -3,48 +3,48 @@
#define __SIMPLE_DEVICE__
#include <types.h>
+#include <commonlib/helpers.h>
#include <device/device.h>
#include <device/pci_ops.h>
#include "ironlake.h"
-unsigned long acpi_fill_mcfg(unsigned long current)
+static int decode_pcie_bar(u32 *const base, u32 *const len)
{
- u32 pciexbar = 0;
- u32 pciexbar_reg;
- int max_buses;
+ *base = 0;
+ *len = 0;
- pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
+ const u32 pciexbar_reg = pci_read_config32(QPI_SAD, SAD_PCIEXBAR);
- // MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))
- return current;
+ return 0;
switch ((pciexbar_reg >> 1) & 3) {
- case 0: // 256MB
- pciexbar =
- pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
- (1 << 28));
- max_buses = 256;
- break;
- case 1: // 128M
- pciexbar =
- pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
- (1 << 28) | (1 << 27));
- max_buses = 128;
- break;
- case 2: // 64M
- pciexbar =
- pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
- (1 << 28) | (1 << 27) | (1 << 26));
- max_buses = 64;
- break;
- default: // RSVD
- return current;
+ case 0: /* 256MB */
+ *base = pciexbar_reg & (0x0f << 28);
+ *len = 256 * MiB;
+ return 1;
+ case 1: /* 128M */
+ *base = pciexbar_reg & (0x1f << 27);
+ *len = 128 * MiB;
+ return 1;
+ case 2: /* 64M */
+ *base = pciexbar_reg & (0x3f << 26);
+ *len = 64 * MiB;
+ return 1;
}
- if (!pciexbar)
+ return 0;
+}
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ u32 length, pciexbar;
+
+ if (!decode_pcie_bar(&pciexbar, &length))
return current;
+ const int max_buses = length / MiB;
+
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1);