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authorJonas Loeffelholz <Jonas.Loeffelholz@9elements.com>2020-06-25 13:50:58 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-07-01 05:22:29 +0000
commitd7238eb5180da0272be4212a9c6c54c685234b99 (patch)
treecf71eac1c3727882e81d2d789e0ecdac9b262648
parentabd3cae588856afa4bebac2d100ca22f61a17175 (diff)
downloadcoreboot-d7238eb5180da0272be4212a9c6c54c685234b99.tar.xz
soc/intel/cannonlake: make satahotplug user configurable via devicetree
Hook up the FSP UPD Change-Id: I6b479bfc83492440eac97cdc8dcc560b6abf4fdf Signed-off-by: Jonas Loeffelholz <Jonas.Loeffelholz@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42803 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-rw-r--r--src/soc/intel/cannonlake/chip.h1
-rw-r--r--src/soc/intel/cannonlake/fsp_params.c4
2 files changed, 5 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 57922e131c..2923efc555 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -147,6 +147,7 @@ struct soc_intel_cannonlake_config {
uint8_t SataPortsEnable[8];
uint8_t SataPortsDevSlp[8];
uint8_t SataPortsDevSlpResetConfig[8];
+ uint8_t SataPortsHotPlug[8];
/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
uint8_t SlpS0WithGbeSupport;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index bd2d7fc2d6..3794ffd0b1 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -297,6 +297,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
sizeof(params->SataPortsEnable));
memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
sizeof(params->SataPortsDevSlp));
+
+ memcpy(params->SataPortsHotPlug, config->SataPortsHotPlug,
+ sizeof(params->SataPortsHotPlug));
+
#if CONFIG(SOC_INTEL_COMETLAKE)
memcpy(params->SataPortsDevSlpResetConfig,
config->SataPortsDevSlpResetConfig,