diff options
| author | Felix Singer <felix.singer@secunet.com> | 2020-08-19 14:13:15 +0200 |
|---|---|---|
| committer | Michael Niewöhner <c0d3z3r0@review.coreboot.org> | 2020-09-04 11:50:30 +0000 |
| commit | d9e459428de519c89b23f9a7465bcb7b835c08a0 (patch) | |
| tree | 956464b00cdcfdc67de63e304ece77fe2b8d249d | |
| parent | 5127cb8b16654a10cc06942be1574bae86804348 (diff) | |
| download | coreboot-d9e459428de519c89b23f9a7465bcb7b835c08a0.tar.xz | |
soc/intel/cnl: Enable HECI3 depending on devicetree
Currently HECI3 gets enabled by the option Heci3Enabled, but this
duplicates the devicetree on/off options. Therefore depend on the
devicetree for enablement of the HECI3 controller.
All corresponding mainboards were checked if the devicetree
configuration matches the Heci3Enabled setting, and divergent
devicetrees were adjusted.
Change-Id: Ic7d52096aee225c2ced1e1bc29ca850fe5073edc
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44579
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
| -rw-r--r-- | src/mainboard/prodrive/hermes/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/purism/librem_whl/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/system76/lemp9/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/chip.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/fsp_params.c | 3 |
5 files changed, 5 insertions, 9 deletions
diff --git a/src/mainboard/prodrive/hermes/devicetree.cb b/src/mainboard/prodrive/hermes/devicetree.cb index 69323f28c4..5615554208 100644 --- a/src/mainboard/prodrive/hermes/devicetree.cb +++ b/src/mainboard/prodrive/hermes/devicetree.cb @@ -28,7 +28,7 @@ chip soc/intel/cannonlake register "HeciEnabled" = "1" end device pci 16.1 on end # Management Engine Interface 2 - device pci 16.4 on end # Management Engine Interface 3 + device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 on end # SATA device pci 1d.6 on # PCIe root port 15 device pci 00.0 on # Aspeed PCI Bridge diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb index fc3f418c6f..b85e10f402 100644 --- a/src/mainboard/purism/librem_whl/devicetree.cb +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -277,9 +277,7 @@ chip soc/intel/cannonlake device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off # Management Engine Interface 3 - register "Heci3Enabled" = "0" - end + device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb index c07b6873e6..e9e3aa30b8 100644 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ b/src/mainboard/system76/lemp9/devicetree.cb @@ -201,9 +201,7 @@ chip soc/intel/cannonlake device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off # Management Engine Interface 3 - register "Heci3Enabled" = "0" - end + device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 device pci 17.0 on end # SATA device pci 19.0 off end # I2C #4 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index e5ceac9312..9e7aa45eda 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -228,7 +228,6 @@ struct soc_intel_cannonlake_config { uint8_t PchIshEnable; /* Heci related */ - uint8_t Heci3Enabled; uint8_t DisableHeciRetry; /* Gfx related */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 51ed2a8b57..615a94f32e 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -525,7 +525,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) else params->ScsUfsEnabled = dev->enabled; - params->Heci3Enabled = config->Heci3Enabled; + dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); + params->Heci3Enabled = is_dev_enabled(dev); #if !CONFIG(HECI_DISABLE_USING_SMM) dev = pcidev_path_on_root(PCH_DEVFN_CSE); params->Heci1Disabled = !is_dev_enabled(dev); |