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authorFelix Held <felix-coreboot@felixheld.de>2015-11-06 18:32:43 +0100
committerStefan Reinauer <stefan.reinauer@coreboot.org>2015-11-19 02:43:23 +0100
commitdf95b51ab636f78f66c27d7a7b0aebf245f288c1 (patch)
tree970d2e6ac1b46684cb0e142d6b81676a6c5ff995
parentb06015b92ec0a44646d18ec32f2cb333e965e616 (diff)
downloadcoreboot-df95b51ab636f78f66c27d7a7b0aebf245f288c1.tar.xz
pcengines/apu1: enable use of clkreq pins
only enable pcie gpp clocks when the corresponding clkreq pin is asserted Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12353 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
-rw-r--r--src/mainboard/pcengines/apu1/mainboard.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c
index 82cf9921a5..f91e8799d8 100644
--- a/src/mainboard/pcengines/apu1/mainboard.c
+++ b/src/mainboard/pcengines/apu1/mainboard.c
@@ -187,10 +187,10 @@ static void mainboard_enable(device_t dev)
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
/* GPP CLK0-2 are connected to the 3 ethernet chips
* GPP CLK3-4 are connected to the miniPCIe slots */
- write8(misc_mem_clk_cntrl + 0, 0xFF);
- write8(misc_mem_clk_cntrl + 1, 0xFF);
+ write8(misc_mem_clk_cntrl + 0, 0x21);
+ write8(misc_mem_clk_cntrl + 1, 0x43);
/* GPP CLK5 is only connected to test pads -> disable */
- write8(misc_mem_clk_cntrl + 2, 0x0F);
+ write8(misc_mem_clk_cntrl + 2, 0x05);
/* disable unconnected GPP CLK6-8 and SLT_GFX_CLK */
write8(misc_mem_clk_cntrl + 3, 0x00);
write8(misc_mem_clk_cntrl + 4, 0x00);