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authorMyles Watson <mylesgw@gmail.com>2010-09-02 20:30:31 +0000
committerMyles Watson <mylesgw@gmail.com>2010-09-02 20:30:31 +0000
commitdfe8d766fb5a561fb8b27007f5802c255f20167b (patch)
tree832a4670d3b1f1fc505df5bab1500f8afd0395ef
parent7f072fe564e1ffb8f91ad6c2acb6855d3a6c1f8f (diff)
downloadcoreboot-dfe8d766fb5a561fb8b27007f5802c255f20167b.tar.xz
Trivial warning fix for adl855pc.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5766 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-rw-r--r--src/northbridge/intel/i855/raminit.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index e611d8e62b..604a5e1f59 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -872,10 +872,14 @@ static void spd_set_dram_throttle_control(const struct mem_controller *ctrl)
static void spd_update(const struct mem_controller *ctrl, u8 reg, u32 new_value)
{
+#if CONFIG_DEBUG_RAM_SETUP
u32 value1 = pci_read_config32(ctrl->d0, reg);
+#endif
pci_write_config32(ctrl->d0, reg, new_value);
+#if CONFIG_DEBUG_RAM_SETUP
u32 value2 = pci_read_config32(ctrl->d0, reg);
PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2);
+#endif
}
/* if ram still doesn't work do this function */