summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-07-22 00:40:21 +0200
committerAngel Pons <th3fanbus@gmail.com>2020-07-24 14:29:36 +0000
commite4c0555230dd284277dc60c4fbfea6d71a48d2a6 (patch)
tree9738756d43331bec5ccaaad13a6c977f6562ed83
parent1e1515fc9d26a77c088985a22344f6b32d95026a (diff)
downloadcoreboot-e4c0555230dd284277dc60c4fbfea6d71a48d2a6.tar.xz
nb/intel/ironlake: Move southbridge code to ibexpeak
There's no need to set up the southbridge in the northbridge code. Change-Id: I0f80c92aca885812c27a8803c2745844d8dfb939 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
-rw-r--r--src/northbridge/intel/ironlake/early_init.c20
-rw-r--r--src/southbridge/intel/ibexpeak/early_pch.c21
-rw-r--r--src/southbridge/intel/ibexpeak/pch.h1
3 files changed, 23 insertions, 19 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c
index e6e9ace211..34ae6c1d19 100644
--- a/src/northbridge/intel/ironlake/early_init.c
+++ b/src/northbridge/intel/ironlake/early_init.c
@@ -15,25 +15,6 @@
static void ironlake_setup_bars(void)
{
- /* Setting up Southbridge. In the northbridge code. */
- printk(BIOS_DEBUG, "Setting up static southbridge registers...");
- pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
-
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- /* Enable ACPI BAR */
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);
-
- printk(BIOS_DEBUG, " done.\n");
-
- printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
- /* No reset */
- RCBA32(GCS) = RCBA32(GCS) | (1 << 5);
- /* halt timer */
- outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
- /* halt timer */
- outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
- printk(BIOS_DEBUG, " done.\n");
-
printk(BIOS_DEBUG, "Setting up static northbridge registers...");
/* Set up all hardcoded northbridge BARs */
pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
@@ -112,6 +93,7 @@ void ironlake_early_initialization(int chipset_type)
}
/* Setup all BARs required for early PCIe and raminit */
+ ibexpeak_setup_bars();
ironlake_setup_bars();
s3_resume = (inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
diff --git a/src/southbridge/intel/ibexpeak/early_pch.c b/src/southbridge/intel/ibexpeak/early_pch.c
index f1c7bb10e1..d9ac0095ee 100644
--- a/src/southbridge/intel/ibexpeak/early_pch.c
+++ b/src/southbridge/intel/ibexpeak/early_pch.c
@@ -25,6 +25,27 @@ static void pch_default_disable(void)
RCBA32(FD2) = 1;
}
+void ibexpeak_setup_bars(void)
+{
+ printk(BIOS_DEBUG, "Setting up static southbridge registers...");
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
+
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+ /* Enable ACPI BAR */
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80);
+
+ printk(BIOS_DEBUG, " done.\n");
+
+ printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+ /* No reset */
+ RCBA32(GCS) = RCBA32(GCS) | (1 << 5);
+ /* halt timer */
+ outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);
+ /* halt timer */
+ outw(inw(DEFAULT_PMBASE | 0x60 | 0x06) | 2, DEFAULT_PMBASE | 0x60 | 0x06);
+ printk(BIOS_DEBUG, " done.\n");
+}
+
void early_pch_init(void)
{
early_gpio_init();
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index 437259ca9b..7c2e2a9f7d 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -38,6 +38,7 @@
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
void enable_usb_bar(void);
+void ibexpeak_setup_bars(void);
void early_pch_init(void);
void early_thermal_init(void);