diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-19 17:01:24 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-20 10:58:28 +0000 |
| commit | e51d731abcd25dee546508e28ba58dd205e3b3f1 (patch) | |
| tree | 384db4384acc220cb5eea1688ff47d2e4eccd294 | |
| parent | ee424e5941a526d354409d943bae374c8b59d68a (diff) | |
| download | coreboot-e51d731abcd25dee546508e28ba58dd205e3b3f1.tar.xz | |
sb/amd/cimx/sb900: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Id634edd7005db85690cdc93579c1f97588ffc5f8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/late.c | 10 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/lpc.c | 6 | ||||
| -rw-r--r-- | src/southbridge/amd/cimx/sb900/lpc.h | 6 |
3 files changed, 11 insertions, 11 deletions
diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 7c001d9b6a..e792fe3c61 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -14,7 +14,7 @@ */ -#include <device/device.h> /* device_t */ +#include <device/device.h> #include <device/pci.h> /* device_operations */ #include <device/pci_ids.h> #include <device/smbus.h> /* smbus_bus_operations */ @@ -73,7 +73,7 @@ static struct pci_operations lops_pci = { .set_subsystem = 0, }; -static void lpc_enable_resources(device_t dev) +static void lpc_enable_resources(struct device *dev) { printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n"); @@ -82,7 +82,7 @@ static void lpc_enable_resources(device_t dev) printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n"); } -static void lpc_init(device_t dev) +static void lpc_init(struct device *dev) { printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n"); /* SB Configure HPET base and enable bit */ @@ -266,7 +266,7 @@ static const struct pci_driver gec_driver __pci_driver = { }; -static void pcie_init(device_t dev) +static void pcie_init(struct device *dev) { printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n"); //- sbPcieGppLateInit(sb_config); @@ -333,7 +333,7 @@ static const struct pci_driver PORTD_driver __pci_driver = { /** * @brief SB Cimx entry point sbBeforePciInit wrapper */ -static void sb900_enable(device_t dev) +static void sb900_enable(struct device *dev) { u8 gpp_port = 0; struct southbridge_amd_cimx_sb900_config *sb_chip = diff --git a/src/southbridge/amd/cimx/sb900/lpc.c b/src/southbridge/amd/cimx/sb900/lpc.c index eb3a73ec89..64b6aa51de 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.c +++ b/src/southbridge/amd/cimx/sb900/lpc.c @@ -19,7 +19,7 @@ #include <arch/ioapic.h> -void lpc_read_resources(device_t dev) +void lpc_read_resources(struct device *dev) { struct resource *res; @@ -73,7 +73,7 @@ void lpc_set_resources(struct device *dev) * @param dev the device whose children's resources are to be enabled * */ -void lpc_enable_childrens_resources(device_t dev) +void lpc_enable_childrens_resources(struct device *dev) { struct bus *link; u32 reg, reg_x; @@ -85,7 +85,7 @@ void lpc_enable_childrens_resources(device_t dev) reg_x = pci_read_config32(dev, 0x48); for (link = dev->link_list; link; link = link->next) { - device_t child; + struct device *child; for (child = link->children; child; child = child->sibling) { if (child->enabled diff --git a/src/southbridge/amd/cimx/sb900/lpc.h b/src/southbridge/amd/cimx/sb900/lpc.h index 75ed4c795f..3fc5404a9f 100644 --- a/src/southbridge/amd/cimx/sb900/lpc.h +++ b/src/southbridge/amd/cimx/sb900/lpc.h @@ -20,8 +20,8 @@ #define SPI_ROM_ENABLE 0x02 #define SPI_BASE_ADDRESS 0xFEC10000 -void lpc_read_resources(device_t dev); -void lpc_set_resources(device_t dev); -void lpc_enable_childrens_resources(device_t dev); +void lpc_read_resources(struct device *dev); +void lpc_set_resources(struct device *dev); +void lpc_enable_childrens_resources(struct device *dev); #endif |