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authorAaron Durbin <adurbin@chromium.org>2016-01-25 17:56:43 -0600
committerPatrick Georgi <pgeorgi@google.com>2016-02-04 17:42:20 +0100
commitf52fb2f7503373adf8a841608f9cb295448ae086 (patch)
treed3266836dcdefdef487879e5a2e4962ae947af8b
parent0f9d5c454b445051d0b8e36004e51b8475ea7c1a (diff)
downloadcoreboot-f52fb2f7503373adf8a841608f9cb295448ae086.tar.xz
google/lars: perform early init for CAR *stage
In order to support both separate verstage and a verified boot after romstage one needs to ensure the proper GPIO and EC configuration been complete. Therefore, move that logic to car_mainboard_post_console_init() in car.c file which gets called in the early flow of a CAR stage (either verstage or romstage). BUG=chrome-os-partner:44827 BRANCH=glados TEST=None Change-Id: I331f25ad4764cab972af7198f6154f604d2dbeae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 2c1cb04645cbf34696e6adf48acec9d396e87ca9 Original-Change-Id: I8d14ea16b2d07bbf04c5c33e4205a85d9f21847b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/324075 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/13585 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
-rw-r--r--src/mainboard/google/lars/Makefile.inc3
-rw-r--r--src/mainboard/google/lars/car.c35
-rw-r--r--src/mainboard/google/lars/romstage.c16
3 files changed, 38 insertions, 16 deletions
diff --git a/src/mainboard/google/lars/Makefile.inc b/src/mainboard/google/lars/Makefile.inc
index 79a26057e4..4bf6e0ab41 100644
--- a/src/mainboard/google/lars/Makefile.inc
+++ b/src/mainboard/google/lars/Makefile.inc
@@ -17,6 +17,7 @@
subdirs-y += spd
romstage-y += boardid.c
+romstage-y += car.c
romstage-y += pei_data.c
verstage-$(CONFIG_CHROMEOS) += chromeos.c
@@ -31,3 +32,5 @@ ramstage-y += pei_data.c
ramstage-y += ramstage.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+verstage-y += car.c
diff --git a/src/mainboard/google/lars/car.c b/src/mainboard/google/lars/car.c
new file mode 100644
index 0000000000..7791b92980
--- /dev/null
+++ b/src/mainboard/google/lars/car.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <ec/google/chromeec/ec.h>
+#include <fsp/car.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't be. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void car_mainboard_post_console_init(void)
+{
+ /* Ensure the EC and PD are in the right mode for recovery */
+ google_chromeec_early_init();
+
+ early_config_gpio();
+}
diff --git a/src/mainboard/google/lars/romstage.c b/src/mainboard/google/lars/romstage.c
index 1d25c7fad9..84c2b6f534 100644
--- a/src/mainboard/google/lars/romstage.c
+++ b/src/mainboard/google/lars/romstage.c
@@ -15,10 +15,7 @@
* GNU General Public License for more details.
*/
-#include <cbfs.h>
-#include <console/console.h>
#include <string.h>
-#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/pei_data.h>
#include <soc/pei_wrapper.h>
@@ -26,14 +23,6 @@
#include "gpio.h"
#include "spd/spd.h"
-static void early_config_gpio(void)
-{
- /* This is a hack for FSP because it does things in MemoryInit()
- * which it shouldn't be. We have to prepare certain gpios here
- * because of the brokenness in FSP. */
- gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
-}
-
void mainboard_romstage_entry(struct romstage_params *params)
{
/* PCH_MEM_CFG[3:0] */
@@ -44,11 +33,6 @@ void mainboard_romstage_entry(struct romstage_params *params)
GPIO_MEM_CONFIG_3,
};
- /* Ensure the EC and PD are in the right mode for recovery */
- google_chromeec_early_init();
-
- early_config_gpio();
-
params->pei_data->mem_cfg_id = gpio_base2_value(spd_gpios,
ARRAY_SIZE(spd_gpios));
/* Fill out PEI DATA */