mediatek: Add SPI tick_dly setting

Add spi tick_dly setting for high-speed spi xfer.

BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot

Change-Id: Ie49fc3efe2a4a6dcdf2a2fc4c91b47e35d4f086e
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

9 files changed, 33 insertions, 12 deletions

diff --git a/src/mainboard/google/kukui/bootblock.c b/src/mainboard/google/kukui/bootblock.c
index 9a7e71c292..ebd1e18d15 100644
--- a/src/mainboard/google/kukui/bootblock.c
+++ b/src/mainboard/google/kukui/bootblock.c
@@ -19,8 +19,11 @@
 
 void bootblock_mainboard_init(void)
 {
-	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz);
-	mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz);
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 6 * MHz,
+		     0);
+	mtk_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK, 26 * MHz,
+		     0);
 	gpio_set_spi_driving(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, SPI_PAD0_MASK,
 			     10);
+
 }
diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c
index 1193bb3fe9..7eee080412 100644
--- a/src/mainboard/google/kukui/early_init.c
+++ b/src/mainboard/google/kukui/early_init.c
@@ -34,6 +34,6 @@ void mainboard_early_init(void)
 
 	gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0);
 
-	mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz);
+	mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0);
 	gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
 }
diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c
index 3c50389914..89169ef0bf 100644
--- a/src/mainboard/google/oak/bootblock.c
+++ b/src/mainboard/google/oak/bootblock.c
@@ -89,7 +89,8 @@ void bootblock_mainboard_init(void)
 	if (CONFIG(OAK_HAS_TPM2))
 		gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING);
 
-	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz);
+	mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD1_MASK, 6*MHz,
+		     0);
 
 	setup_chromeos_gpios();
 
diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h
index 162db59f94..81a9098180 100644
--- a/src/soc/mediatek/common/include/soc/spi_common.h
+++ b/src/soc/mediatek/common/include/soc/spi_common.h
@@ -84,8 +84,9 @@ extern struct mtk_spi_bus spi_bus[];
 
 void mtk_spi_set_gpio_pinmux(unsigned int bus,
 			     enum spi_pad_mask pad_select);
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks);
+void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
+			unsigned int tick_dly);
 void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
-		  unsigned int speed_hz);
+		  unsigned int speed_hz, unsigned int tick_dly);
 
 #endif
diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c
index 71ed95a228..1af6f105c3 100644
--- a/src/soc/mediatek/common/spi.c
+++ b/src/soc/mediatek/common/spi.c
@@ -53,7 +53,7 @@ static void spi_sw_reset(struct mtk_spi_regs *regs)
 }
 
 void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
-		  unsigned int speed_hz)
+		  unsigned int speed_hz, unsigned int tick_dly)
 {
 	u32 div, sck_ticks, cs_ticks;
 
@@ -73,7 +73,7 @@ void mtk_spi_init(unsigned int bus, enum spi_pad_mask pad_select,
 	printk(BIOS_DEBUG, "SPI%u(PAD%u) initialized at %u Hz\n",
 	       bus, pad_select, SPI_HZ / (sck_ticks * 2));
 
-	mtk_spi_set_timing(regs, sck_ticks, cs_ticks);
+	mtk_spi_set_timing(regs, sck_ticks, cs_ticks, tick_dly);
 
 	clrsetbits_le32(&regs->spi_cmd_reg,
 			(SPI_CMD_CPHA_EN | SPI_CMD_CPOL_EN |
diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h
index aaef3aa25c..58bf517f9d 100644
--- a/src/soc/mediatek/mt8173/include/soc/spi.h
+++ b/src/soc/mediatek/mt8173/include/soc/spi.h
@@ -43,4 +43,9 @@ enum {
 	SPI_CFG0_CS_SETUP_SHIFT = 24,
 };
 
+enum {
+	SPI_CFG1_TICK_DLY_SHIFT = 30,
+	SPI_CFG1_TICK_DLY_MASK = 0x3 << SPI_CFG1_TICK_DLY_SHIFT,
+};
+
 #endif
diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c
index 0cc8377ff4..d0094418b8 100644
--- a/src/soc/mediatek/mt8173/spi.c
+++ b/src/soc/mediatek/mt8173/spi.c
@@ -38,14 +38,17 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus,
 	gpio_set_mode(GPIO(MSDC2_CMD), PAD_MSDC2_CMD_FUNC_SPI_CS_1);
 }
 
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks)
+void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
+			unsigned int tick_dly)
 {
 	write32(&regs->spi_cfg0_reg,
 		((sck_ticks - 1) << SPI_CFG0_SCK_HIGH_SHIFT) |
 		((sck_ticks - 1) << SPI_CFG0_SCK_LOW_SHIFT) |
 		((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
 		((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT));
-	clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK,
+	clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK |
+			SPI_CFG1_TICK_DLY_MASK,
+			(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
 			((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
 }
 
diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h
index 9bc7121847..f718081f67 100644
--- a/src/soc/mediatek/mt8183/include/soc/spi.h
+++ b/src/soc/mediatek/mt8183/include/soc/spi.h
@@ -49,5 +49,10 @@ enum {
 	SPI_CFG2_SCK_HIGH_SHIFT = 16,
 };
 
+enum {
+	SPI_CFG1_TICK_DLY_SHIFT = 29,
+	SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT,
+
+};
 
 #endif
diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c
index a79dafba94..982f6439ed 100644
--- a/src/soc/mediatek/mt8183/spi.c
+++ b/src/soc/mediatek/mt8183/spi.c
@@ -109,7 +109,8 @@ void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select)
 		gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func);
 }
 
-void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks)
+void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks,
+			unsigned int tick_dly)
 {
 	write32(&regs->spi_cfg0_reg,
 		((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) |
@@ -119,7 +120,9 @@ void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks)
 		((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) |
 		((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT));
 
-	clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_CS_IDLE_MASK,
+	clrsetbits_le32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK |
+			SPI_CFG1_CS_IDLE_MASK,
+			(tick_dly << SPI_CFG1_TICK_DLY_SHIFT) |
 			((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT));
 }