mb/asus/p5qc: Add ASUS P5Q as a variant (with documentation)

Change-Id: I6c7bbb89af88cce1a53c21a4b4d8bc1c284e1cb2
Signed-off-by: Ivan Vatlin <jenrus@tuta.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

4 files changed, 207 insertions, 2 deletions

diff --git a/Documentation/mainboard/asus/p5q.md b/Documentation/mainboard/asus/p5q.md
new file mode 100644
index 0000000000..bce71e8786
--- /dev/null
+++ b/Documentation/mainboard/asus/p5q.md
@@ -0,0 +1,77 @@
+# ASUS P5Q
+
+This page describes how to run coreboot on the [ASUS P5Q] desktop board.
+
+## TODO
+
+The following things are working in this coreboot port:
+
++ PCI slots
++ PCI-e slots
++ Onboard Ethernet
++ USB
++ Onboard sound card
++ PS/2 keyboard
++ All 4 DIMM slots
++ S3 suspend and resume
++ Red SATA ports
+
+The following things are still missing from this coreboot port:
+
++ PS/2 mouse support
++ PATA aka IDE (because of buggy IDE controller)
++ Fan control (will be working on 100% power)
++ TPM module (support not implemented)
+
+The following things are untested on this coreboot port:
+
++ S/PDIF
++ CD Audio In
++ Floppy disk drive
++ FireWire: PCI device shows up and driver loads, no further test
+
+
+## Flashing coreboot
+
+```eval_rst
++-------------------+----------------+
+| Type              | Value          |
++===================+================+
+| Socketed flash    | Yes            |
++-------------------+----------------+
+| Model             | MX25L8005      |
++-------------------+----------------+
+| Size              | 1 MiB          |
++-------------------+----------------+
+| Package           | Socketed DIP-8 |
++-------------------+----------------+
+| Write protection  | No             |
++-------------------+----------------+
+| Dual BIOS feature | No             |
++-------------------+----------------+
+| Internal flashing | Yes            |
++-------------------+----------------+
+```
+
+You can flash coreboot into your motherboard using [this guide].
+
+## Technology
+
+```eval_rst
++------------------+---------------------------------------------------+
+| Northbridge      | Intel P45 (called x4x in coreboot code)           |
++------------------+---------------------------------------------------+
+| Southbridge      | Intel ICH10R (called i82801jx in coreboot code)   |
++------------------+---------------------------------------------------+
+| CPU (LGA775)     | Model f4x, f6x, 6fx, 1067x (Pentium 4, d, Core 2) |
++------------------+---------------------------------------------------+
+| SuperIO          | Winbond W83667HG                                  |
++------------------+---------------------------------------------------+
+| Coprocessor      | No                                                |
++------------------+---------------------------------------------------+
+| Clockgen (CK505) | ICS 9LPRS918JKLF                                  |
++------------------+---------------------------------------------------+
+```
+
+[ASUS P5Q]: https://www.asus.com/Motherboards/P5Q
+[this guide]: https://doc.coreboot.org/flash_tutorial/int_flashrom.html
diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig
index b59cd3cd44..e7d23bdaac 100644
--- a/src/mainboard/asus/p5qc/Kconfig
+++ b/src/mainboard/asus/p5qc/Kconfig
@@ -1,8 +1,9 @@
 #
 # This file is part of the coreboot project.
 #
-# Copyright (C) 2015 Damien Zammit <damien@zamaudio.com>
+# Copyright (C) 2015 Damien Zammit  <damien@zamaudio.com>
 # Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
+# Copyright (C) 2019 Ivan Vatlin    <jenrus@tuta.io>
 #
 # This program is free software; you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -14,7 +15,7 @@
 # GNU General Public License for more details.
 #
 
-if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO
+if BOARD_ASUS_P5QC || BOARD_ASUS_P5Q_PRO || BOARD_ASUS_P5QL_PRO || BOARD_ASUS_P5Q
 
 config BOARD_SPECIFIC_OPTIONS
 	def_bool y
@@ -38,12 +39,14 @@ config VARIANT_DIR
 	default "p5qc" if BOARD_ASUS_P5QC
 	default "p5q_pro" if BOARD_ASUS_P5Q_PRO
 	default "p5ql_pro" if BOARD_ASUS_P5QL_PRO
+	default "p5q" if BOARD_ASUS_P5Q
 
 config MAINBOARD_PART_NUMBER
 	string
 	default "P5QC" if BOARD_ASUS_P5QC
 	default "P5Q PRO" if BOARD_ASUS_P5Q_PRO
 	default "P5QL PRO" if BOARD_ASUS_P5QL_PRO
+	default "P5Q" if BOARD_ASUS_P5Q
 
 config DEVICETREE
 	string
diff --git a/src/mainboard/asus/p5qc/Kconfig.name b/src/mainboard/asus/p5qc/Kconfig.name
index 2a3503690f..22c0ccabbd 100644
--- a/src/mainboard/asus/p5qc/Kconfig.name
+++ b/src/mainboard/asus/p5qc/Kconfig.name
@@ -6,3 +6,6 @@ config BOARD_ASUS_P5Q_PRO
 
 config BOARD_ASUS_P5QL_PRO
 	bool "P5QL PRO"
+
+config BOARD_ASUS_P5Q
+	bool "P5Q"
diff --git a/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb
new file mode 100644
index 0000000000..a1211ccd29
--- /dev/null
+++ b/src/mainboard/asus/p5qc/variants/p5q/devicetree.cb
@@ -0,0 +1,122 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Damien Zammit  <damien@zamaudio.com>
+# Copyright (C) 2018 Arthur Heymans <arthur@aheymans.xyz>
+# Copyright (C) 2019 Ivan Vatlin    <jenrus@tuta.io>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+chip northbridge/intel/x4x		# Northbridge
+	device cpu_cluster 0 on		# APIC cluster
+		chip cpu/intel/socket_LGA775
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_1067x		# CPU
+			device lapic 0xACAC off end
+		end
+	end
+	device domain 0 on		# PCI domain
+		device pci 0.0 on  end		# Host Bridge
+		device pci 1.0 on  end		# PEG
+		device pci 6.0 off end		# PEG 2
+		chip southbridge/intel/i82801jx	# Southbridge
+			register "gpe0_en" = "0x40"
+
+			# Enable all six SATA ports.
+			register "sata_port_map"	= "0x3f"
+
+			# Enable PCIe ports 0,2,3 as slots.
+			register "pcie_slot_implemented"	= "0x31"
+
+			register "gen1_dec" = "0x00000295"
+			register "gen2_dec" = "0x001c4701"
+
+			device pci 19.0 off end		# GBE
+			device pci 1a.0 on  end		# USB
+			device pci 1a.1 on  end		# USB
+			device pci 1a.2 on  end		# USB
+			device pci 1a.7 on  end		# USB
+			device pci 1b.0 on  end		# Audio
+			device pci 1c.0 on  end		# PCIe 1: PCIEX1_1 slot
+			device pci 1c.1 on  end		# PCIe 2: PCIEX1_2 slot
+			device pci 1c.2 off end		# PCIe 3: Unconnected
+			device pci 1c.3 off end		# PCIe 4: Unconnected
+			device pci 1c.4 on  end		# PCIe 5: Marvell 88SE6121 IDE/SATA controller
+			device pci 1c.5 on  end		# PCIe 6: Atheros AR8121 Ethernet NIC
+			device pci 1d.0 on  end		# USB
+			device pci 1d.1 on  end		# USB
+			device pci 1d.2 on  end		# USB
+			device pci 1d.7 on  end		# USB
+			device pci 1e.0 on  end		# PCI bridge
+			device pci 1f.0 on   		# LPC bridge
+				chip superio/winbond/w83667hg-a	# Super I/O
+					device pnp 2e.0 on		# FDC
+						# Global registers
+						irq 0x2a = 0x00
+						irq 0x2c = 0x22
+						irq 0x2d = 0x00
+						# Floppy
+						io 0x60  = 0x3f0
+						irq 0xf0 = 0x0e
+					end
+					device pnp 2e.1 off end		# LPT1
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2
+					device pnp 2e.5 on		# PS/2 keyboard & mouse
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.106 off end	# SPI1
+					device pnp 2e.107 off end	# GPIO6
+					device pnp 2e.207 off end	# GPIO7
+					device pnp 2e.307 on		# GPIO8
+						irq 0xe4 = 0xfb
+					end
+					device pnp 2e.407 off end	# GPIO9
+					device pnp 2e.8   off end	# WDT
+					device pnp 2e.108 off end	# GPIO1
+					device pnp 2e.9   off end	# GPIO2
+					device pnp 2e.109 on  end	# GPIO3
+					device pnp 2e.209 on		# GPIO4
+						irq 0xf0 = 0x7f
+						irq 0xfe = 0x07
+					end
+					device pnp 2e.309 on end	# GPIO5
+					device pnp 2e.a   on		# ACPI
+						irq 0xe4 = 0x10 # 3VSBSW# enable
+						irq 0xe5 = 0x02
+						irq 0xf2 = 0xfc
+					end
+					device pnp 2e.b on		# HW Monitor
+						io 0x60 = 0x290
+						irq 0x70 = 0
+						# IRQ purposefully not assigned to prevent lockups
+					end
+					device pnp 2e.c on end		# PECI
+					device pnp 2e.d on end		# VID_BUSSEL
+					device pnp 2e.f on end		# GPIO_PP_OD
+				end
+			end
+			device pci 1f.2 on  end		# SATA
+			device pci 1f.3 on  end		# SMbus
+			device pci 1f.4 off end
+			device pci 1f.5 off end		# SATA (legacy mode)
+			device pci 1f.6 off end
+		end
+	end
+end