Intel 82371EB: Add IDE init support.

In a mainboard's Config.lb file you can configure whether the primary
and/or secondary IDE interfaces shall be enabled.

Also, various fixups in the rest of the southbridge code, most notably
the early SMBus code, plus some documentation improvements.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey_osgood@verizon.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 227 insertions, 88 deletions

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 791b8ea528..539ca3ad38 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -1813,6 +1813,11 @@
 #define PCI_DEVICE_ID_INTEL_82371AB	0x7111
 #define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
 #define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
+#define PCI_DEVICE_ID_INTEL_82371AB_ISA		0x7110
+#define PCI_DEVICE_ID_INTEL_82371AB_IDE		0x7111
+#define PCI_DEVICE_ID_INTEL_82371AB_USB		0x7112
+#define PCI_DEVICE_ID_INTEL_82371AB_ACPI	0x7113 /* Same as SMB */
+#define PCI_DEVICE_ID_INTEL_82371AB_SMB		0x7113 /* Same as ACPI */
 #define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
 #define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
 #define PCI_DEVICE_ID_INTEL_82801AA_2	0x2412
diff --git a/src/southbridge/intel/i82371eb/Config.lb b/src/southbridge/intel/i82371eb/Config.lb
index 163e846a10..4958449902 100644
--- a/src/southbridge/intel/i82371eb/Config.lb
+++ b/src/southbridge/intel/i82371eb/Config.lb
@@ -22,4 +22,5 @@ config chip.h
 
 driver i82371eb.o
 driver i82371eb_smbus.o
+driver i82371eb_ide.o
 
diff --git a/src/southbridge/intel/i82371eb/chip.h b/src/southbridge/intel/i82371eb/chip.h
index 58efa3b66f..2dac6d14ec 100644
--- a/src/southbridge/intel/i82371eb/chip.h
+++ b/src/southbridge/intel/i82371eb/chip.h
@@ -1,13 +1,34 @@
-#ifndef I82371EB_CHIP_H
-#define I82371EB_CHIP_H
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
-struct southbridge_intel_i82371eb_config 
-{
-	unsigned int ide0_enable : 1;
-	unsigned int ide1_enable : 1;
-};
+#ifndef SOUTHBRIDGE_INTEL_I82371EB_CHIP_H
+#define SOUTHBRIDGE_INTEL_I82371EB_CHIP_H
+
+#include <device/device.h>
 
-struct chip_operations;
 extern struct chip_operations southbridge_intel_i82371eb_ops;
 
-#endif /* I82371EB_CHIP_H */
+struct southbridge_intel_i82371eb_config {
+	int ide0_enable:1;
+	int ide1_enable:1;
+	int usb_enable:1;
+};
+
+#endif				/* SOUTHBRIDGE_INTEL_I82371EB_CHIP_H */
diff --git a/src/southbridge/intel/i82371eb/i82371eb.c b/src/southbridge/intel/i82371eb/i82371eb.c
index ece071bb7d..ab982cf65a 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.c
+++ b/src/southbridge/intel/i82371eb/i82371eb.c
@@ -33,24 +33,25 @@
 /**
  * Enable access to all BIOS regions. Do not enable write access to the ROM.
  *
- * @param dev TODO
+ * XBCS register bits:
+ * - Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
+ *              FFF00000-FFF7FFFF are forwarded to ISA).
+ * - Set bit 7: Extended BIOS Enable (PCI master accesses to
+ *              FFF80000-FFFDFFFF are forwarded to ISA).
+ * - Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
+ *              the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
+ *              of 1 Mbyte, or the aliases at the top of 4 Gbyte
+ *              (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
+ * - Bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
+ *
+ * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
+ *
+ * @param dev The device to use.
  */
 void i82371eb_enable(device_t dev)
 {
 	uint16_t reg;
 
-	/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
-	 *            FFF00000-FFF7FFFF are forwarded to ISA).
-	 * Set bit 7: Extended BIOS Enable (PCI master accesses to
-	 *            FFF80000-FFFDFFFF are forwarded to ISA).
-	 * Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
-	 *            the lower 64-Kbyte BIOS block (E0000-EFFFF) at the top
-	 *            of 1 Mbyte, or the aliases at the top of 4 Gbyte
-	 *            (FFFE0000-FFFEFFFF) result in the generation of BIOSCS#.
-	 * Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
-	 * Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
-	 */
-
 	reg = pci_read_config16(dev, XBCS);
 	reg |= 0x2c0;
 	pci_write_config16(dev, XBCS, reg);
diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h
index 6db363b857..096f8722df 100644
--- a/src/southbridge/intel/i82371eb/i82371eb.h
+++ b/src/southbridge/intel/i82371eb/i82371eb.h
@@ -18,17 +18,28 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-#ifndef I82371EB_H
-#define I82371EB_H
+#ifndef SOUTHBRIDGE_INTEL_I82371EB_H
+#define SOUTHBRIDGE_INTEL_I82371EB_H
 
 #ifndef __ROMCC__
-
 #include "chip.h"
+void i82371eb_enable(device_t dev);
+#endif
 
+#define PCICMD		0x04	/* PCI Command Register */
 #define XBCS		0x4e	/* X-Bus Chip Select register */
 
-void i82371eb_enable(device_t dev);
+/* SMBus */
+#define SMBBA		0x90	/* SMBus Base Address */
+#define SMBHSTCFG	0xd2	/* SMBus Host Configuration */
 
-#endif
+/* IDE */
+#define IDETIM_PRI	0x40	/* IDE timing register, primary channel */
+#define IDETIM_SEC	0x42	/* IDE timing register, secondary channel */
+
+/* Bit definitions */
+#define	IOSE			(1 << 0)	/* I/O Space Enable */
+#define SMB_HST_EN		(1 << 0)	/* Host Interface Enable */
+#define IDE_DECODE_ENABLE	(1 << 15)	/* IDE Decode Enable */
 
-#endif				/* I82371EB_H */
+#endif				/* SOUTHBRIDGE_INTEL_I82371EB_H */
diff --git a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
index 49be6a49b5..ab0b51e52e 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_early_smbus.c
@@ -1,3 +1,27 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* TODO: Implement smbus_write_byte(), smbus_recv_byte(), smbus_send_byte(). */
+
+#include <device/pci_ids.h>
+#include "i82371eb.h"
 #include "i82371eb_smbus.h"
 
 #define SMBUS_IO_BASE 0x0f00
@@ -5,49 +29,35 @@
 static void enable_smbus(void)
 {
 	device_t dev;
-	dev = pci_locate_device(PCI_ID(0x8086, 0x7113), 0);
+	uint8_t reg8;
+	uint16_t reg16;
+
+	dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL,
+				PCI_DEVICE_ID_INTEL_82371AB_SMB), 0);
+
 	if (dev == PCI_DEV_INVALID) {
-		die("SMBUS controller not found\r\n");
+		die("SMBus controller not found\r\n");
 	}
-	uint8_t enable;
 	print_spew("SMBus controller enabled\r\n");
-	pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1 );
-	// Enable and set SMBBus 
-	// 0x01 Interrupt to SMI# 
-	// (0x4<<1)|1 set interrupt to IRQ9
-	pci_write_config8(dev, 0xd2, (0x4<<1)|1);
-	
-	// Enable the IO space
-	pci_write_config16(dev, 0x04, 1);
-	
-	/* clear any lingering errors, so the transaction will run */
-	outb(0x1e, SMBUS_IO_BASE + SMBHST_STATUS);
-}
 
+	/* Set the SMBus I/O base. */
+	pci_write_config32(dev, SMBBA, SMBUS_IO_BASE | 1);
 
+	/* Enable the SMBus Controller Host Interface. */
+	reg8 = pci_read_config8(dev, SMBHSTCFG);
+	reg8 |= SMB_HST_EN;
+	pci_write_config8(dev, SMBHSTCFG, reg8);
 
-static int smbus_read_byte(unsigned device, unsigned address)
-{
-	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
-}
-
-
-// The following functions are broken.  Do no use until you
-// have fixed the low level code to do the right thing.
-//
-#if 0
-static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
-{
-	return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val);
-}
+	/* Enable access to the SMBus I/O space. */
+	reg16 = pci_read_config16(dev, PCICMD);
+	reg16 |= IOSE;
+	pci_write_config16(dev, PCICMD, reg16);
 
-static int smbus_recv_byte(unsigned device)
-{
-	return do_smbus_recv_byte(SMBUS_IO_BASE, device);
+	/* Clear any lingering errors, so the transaction will run. */
+	outb(inb(SMBUS_IO_BASE + SMBHST_STATUS), SMBUS_IO_BASE + SMBHST_STATUS);
 }
 
-static int smbus_send_byte(unsigned device, unsigned char val)
+static int smbus_read_byte(unsigned int device, unsigned int address)
 {
-	return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
-#endif
diff --git a/src/southbridge/intel/i82371eb/i82371eb_ide.c b/src/southbridge/intel/i82371eb/i82371eb_ide.c
new file mode 100644
index 0000000000..2c5b0c68d2
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_ide.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "i82371eb.h"
+
+/**
+ * Initialize the IDE controller.
+ *
+ * Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
+ * we enable or disable the primary and secondary IDE interface, respectively.
+ *
+ * @param dev The device to use.
+ */
+static void ide_init(struct device *dev)
+{
+	uint16_t reg;
+	struct southbridge_intel_i82371eb_config *conf;
+
+	conf = dev->chip_info;
+
+	/* Enable/disable the primary IDE interface. */
+	reg = pci_read_config16(dev, IDETIM_PRI);
+	if (conf->ide0_enable) {
+		reg |= IDE_DECODE_ENABLE;
+		print_info("Primary IDE interface enabled\n");
+	} else {
+		reg &= ~(IDE_DECODE_ENABLE);
+		print_info("Primary IDE interface disabled\n");
+	}
+	pci_write_config16(dev, IDETIM_PRI, reg);
+
+	/* Enable/disable the secondary IDE interface. */
+	reg = pci_read_config16(dev, IDETIM_SEC);
+	if (conf->ide1_enable) {
+		reg |= IDE_DECODE_ENABLE;
+		print_info("Secondary IDE interface enabled\n");
+	} else {
+		reg &= ~(IDE_DECODE_ENABLE);
+		print_info("Secondary IDE interface disabled\n");
+	}
+	pci_write_config16(dev, IDETIM_SEC, reg);
+}
+
+/* There are no subsystem IDs on the Intel 82371EB. */
+static struct pci_operations lops_pci = {
+	// .set_subsystem = 0,
+};
+
+static struct device_operations ide_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= ide_init,
+	.scan_bus		= 0,
+	.ops_pci		= &lops_pci,
+};
+
+static struct pci_driver ide_driver __pci_driver = {
+	.ops	= &ide_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_IDE,
+};
diff --git a/src/southbridge/intel/i82371eb/i82371eb_smbus.c b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
index 07c4bb07f0..cc47f78649 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_smbus.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_smbus.c
@@ -1,43 +1,50 @@
 /*
- * (C) 2004 Linux Networx
- * (C) 2005 Bitworks
-*/
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
 
-#include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <device/pci_ops.h>
 #include <device/smbus.h>
-#include <arch/io.h>
 #include "i82371eb.h"
 
-
-static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
-{
-	pci_write_config32(dev, 0x44, 
-		((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-
 static struct smbus_bus_operations lops_smbus_bus = {
 };
 
+/* There are no subsystem IDs on the Intel 82371EB. */
 static struct pci_operations lops_pci = {
-	.set_subsystem = lpci_set_subsystem,
+	// .set_subsystem = 0,
 };
+
 static struct device_operations smbus_ops = {
-	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = 0,
-	.scan_bus         = scan_static_bus,
-	.enable           = i82371eb_enable,
-	.ops_pci          = &lops_pci,
-	.ops_smbus_bus    = &lops_smbus_bus,
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= 0,
+	.scan_bus		= scan_static_bus,
+	// .enable		= i82371eb_enable,	// TODO: Needed?
+	.ops_pci		= &lops_pci,
+	.ops_smbus_bus		= &lops_smbus_bus,
 };
 
 static struct pci_driver smbus_driver __pci_driver = {
-	.ops = &smbus_ops,
-	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = 0x7111, // FIXME?
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= PCI_DEVICE_ID_INTEL_82371AB_SMB,
 };