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authorKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-14 09:09:29 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2018-05-15 03:56:51 +0000
commit15a971b89fe23eb92cd3a88bff8726beae87669d (patch)
treefc66ffc3cf0dcb9b8084d32b457dddab8458fe3c
parent8b72aaf3f723c3be348879bb089cc741c4db73ad (diff)
downloadcoreboot-15a971b89fe23eb92cd3a88bff8726beae87669d.tar.xz
util/msrtool: Fix swapped IA32_MC3_x and IA32_MC4_x
Registers IA32_MCi_xx are defined as architectural MSRs since "P6 Family Processors" and should have model-agnostic indexing. Note that in IA32 architecture manual, names of these MSRs are similarly swapped in the table of Intel Core Microarchitecture. I take this is an error in the documentation only, and it got copy-pasted across different CPU family files in the utility. Change-Id: I227102875b5c3d6ac144ed23a3085f3c37dabd4a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/26269 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat
-rw-r--r--util/msrtool/intel_atom.c12
-rw-r--r--util/msrtool/intel_core1.c6
-rw-r--r--util/msrtool/intel_core2_early.c6
-rw-r--r--util/msrtool/intel_core2_later.c16
-rw-r--r--util/msrtool/intel_nehalem.c16
-rw-r--r--util/msrtool/intel_pentium3.c6
-rw-r--r--util/msrtool/intel_pentium3_early.c12
7 files changed, 37 insertions, 37 deletions
diff --git a/util/msrtool/intel_atom.c b/util/msrtool/intel_atom.c
index 39e1676e96..f2df5ae9f9 100644
--- a/util/msrtool/intel_atom.c
+++ b/util/msrtool/intel_atom.c
@@ -200,22 +200,22 @@ const struct msrdef intel_atom_msrs[] = {
{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
- {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT }
}},
- {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT }
}},
- {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT }
}},
diff --git a/util/msrtool/intel_core1.c b/util/msrtool/intel_core1.c
index 039a2f8228..1848698d46 100644
--- a/util/msrtool/intel_core1.c
+++ b/util/msrtool/intel_core1.c
@@ -70,13 +70,13 @@ const struct msrdef intel_core1_msrs[] = {
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
diff --git a/util/msrtool/intel_core2_early.c b/util/msrtool/intel_core2_early.c
index 1072624443..7c6895c7e9 100644
--- a/util/msrtool/intel_core2_early.c
+++ b/util/msrtool/intel_core2_early.c
@@ -88,13 +88,13 @@ const struct msrdef intel_core2_early_msrs[] = {
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
{0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
diff --git a/util/msrtool/intel_core2_later.c b/util/msrtool/intel_core2_later.c
index b61f508b4f..4bb00975f6 100644
--- a/util/msrtool/intel_core2_later.c
+++ b/util/msrtool/intel_core2_later.c
@@ -1093,28 +1093,28 @@ const struct msrdef intel_core2_later_msrs[] = {
{0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
- {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
+ {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
{ BITS_EOT }
}},
- {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT }
}},
- {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT }
}},
- {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT }
}},
- {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
+ {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
{ BITS_EOT }
}},
{0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {
diff --git a/util/msrtool/intel_nehalem.c b/util/msrtool/intel_nehalem.c
index 6f99217f1e..11acdd80d0 100644
--- a/util/msrtool/intel_nehalem.c
+++ b/util/msrtool/intel_nehalem.c
@@ -1657,28 +1657,28 @@ const struct msrdef intel_nehalem_msrs[] = {
{0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
- {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
+ {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
{ BITS_EOT }
}},
- {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT }
}},
- {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT }
}},
- {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT }
}},
- {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
+ {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
{ BITS_EOT }
}},
{0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {
diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c
index 6b12428294..34d38a8870 100644
--- a/util/msrtool/intel_pentium3.c
+++ b/util/msrtool/intel_pentium3.c
@@ -168,13 +168,13 @@ const struct msrdef intel_pentium3_msrs[] = {
{0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
{ MSR_EOT }
diff --git a/util/msrtool/intel_pentium3_early.c b/util/msrtool/intel_pentium3_early.c
index afdc62ec66..f62439de68 100644
--- a/util/msrtool/intel_pentium3_early.c
+++ b/util/msrtool/intel_pentium3_early.c
@@ -234,22 +234,22 @@ const struct msrdef intel_pentium3_early_msrs[] = {
{0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
{ BITS_EOT }
}},
- {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+ {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
{ BITS_EOT }
}},
- {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+ {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
{ BITS_EOT }
}},
- {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+ {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
{ BITS_EOT }
}},
- {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
+ {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
{ BITS_EOT }
}},
- {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
+ {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
{ BITS_EOT }
}},
- {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
+ {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
{ BITS_EOT }
}},
{ MSR_EOT }
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 06:12:57 +0000