Remove the Embedded Planet board.

Signed-off-by: Ronald G. Minnich <rminich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 0 insertions, 491 deletions

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 751eddac78..9f7f8e42d5 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -38,8 +38,6 @@ config VENDOR_DIGITAL_LOGIC
 	bool "DIGITAL-LOGIC"
 config VENDOR_EAGLELION
 	bool "EagleLion"
-config VENDOR_EMBEDDED_PLANET
-	bool "Embedded Planet"
 config VENDOR_EMULATION
 	bool "Emulation"
 config VENDOR_GIGABYTE
@@ -184,11 +182,6 @@ config MAINBOARD_VENDOR
 
 config MAINBOARD_VENDOR
 	string
-	default "Embedded Planet"
-	depends on VENDOR_EMBEDDED_PLANET
-
-config MAINBOARD_VENDOR
-	string
 	default "Emulation"
 	depends on VENDOR_EMULATION
 
@@ -349,7 +342,6 @@ source "src/mainboard/compaq/Kconfig"
 source "src/mainboard/dell/Kconfig"
 source "src/mainboard/digitallogic/Kconfig"
 source "src/mainboard/eaglelion/Kconfig"
-source "src/mainboard/embeddedplanet/Kconfig"
 source "src/mainboard/emulation/Kconfig"
 source "src/mainboard/gigabyte/Kconfig"
 source "src/mainboard/hp/Kconfig"
@@ -361,7 +353,6 @@ source "src/mainboard/jetway/Kconfig"
 source "src/mainboard/kontron/Kconfig"
 source "src/mainboard/lippert/Kconfig"
 source "src/mainboard/mitac/Kconfig"
-source "src/mainboard/motorola/Kconfig"
 source "src/mainboard/msi/Kconfig"
 source "src/mainboard/nec/Kconfig"
 source "src/mainboard/newisys/Kconfig"
diff --git a/src/mainboard/embeddedplanet/Kconfig b/src/mainboard/embeddedplanet/Kconfig
deleted file mode 100644
index 792d600548..0000000000
--- a/src/mainboard/embeddedplanet/Kconfig
+++ /dev/null
@@ -1 +0,0 @@
-#
diff --git a/src/mainboard/embeddedplanet/ep405pc/Config.lb b/src/mainboard/embeddedplanet/ep405pc/Config.lb
deleted file mode 100644
index 4f7f808cec..0000000000
--- a/src/mainboard/embeddedplanet/ep405pc/Config.lb
+++ /dev/null
@@ -1,27 +0,0 @@
-##
-## Config file for the Embedded Planet EP405PC Computing Engine
-##
-
-##
-## Early board initialization, called from ppc_main()
-##
-initobject init.c
-
-arch ppc end
-chip cpu/ppc/ppc4xx 
-	device pci_domain 0 on
-		device pci 0.0 on end
-		chip southbridge/winbond/w83c553 
-			device pci 9.0 on end # ISA bridge
-			device pci 9.1 on end # IDE contoller
-		end
-		device pci e.0 on end
-	end
-end
-	
-##
-## Build the objects we have code for in this directory.
-##
-
-addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
-makedefine CFLAGS += -msoft-float
diff --git a/src/mainboard/embeddedplanet/ep405pc/Options.lb b/src/mainboard/embeddedplanet/ep405pc/Options.lb
deleted file mode 100644
index e91b12136b..0000000000
--- a/src/mainboard/embeddedplanet/ep405pc/Options.lb
+++ /dev/null
@@ -1,153 +0,0 @@
-##
-## Config file for the Embedded Planet EP405PC Computing Engine
-##
-
-uses CONFIG_PCIC0_CFGADDR 
-uses CONFIG_CBFS
-uses CONFIG_ARCH_X86
-uses CONFIG_PCIC0_CFGDATA 
-uses CONFIG_ISA_IO_BASE 
-uses CONFIG_ISA_MEM_BASE 
-uses CONFIG_TTYS0_BASE 
-uses CONFIG_IO_BASE 
-
-uses CONFIG_CPU_OPT
-uses CONFIG_CROSS_COMPILE 
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_COMPRESS 
-uses CONFIG_CHIP_CONFIGURE
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_USE_INIT
-uses CONFIG_CONSOLE_SERIAL8250 
-uses CONFIG_TTYS0_BAUD CONFIG_TTYS0_DIV
-uses CONFIG_NO_POST
-uses CONFIG_IDE
-uses CONFIG_FS_PAYLOAD
-uses CONFIG_FS_EXT2
-uses CONFIG_FS_ISO9660
-uses CONFIG_FS_FAT
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_AUTOBOOT_CMDLINE
-uses CONFIG_SYS_CLK_FREQ
-uses CONFIG_IDE_BOOT_DRIVE
-#uses CONFIG_IDE_SWAB
-uses CONFIG_IDE_OFFSET 
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_RESET
-uses CONFIG_EXCEPTION_VECTORS
-uses CONFIG_ROMBASE
-uses CONFIG_ROMSTART
-uses CONFIG_RAMBASE
-#uses CONFIG_RAMSTART
-uses CONFIG_EMBEDDED_RAM_SIZE
-uses CONFIG_STACK_SIZE CONFIG_HEAP_SIZE
-
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-##
-## Set PCI configuration register addresses
-##
-default CONFIG_PCIC0_CFGADDR=0xeec00000
-default CONFIG_PCIC0_CFGDATA=0xeec00004
-
-##
-## Set PCI/ISA I/O and memory base address
-##
-default CONFIG_ISA_IO_BASE=0xe8000000
-default CONFIG_ISA_MEM_BASE=0x80000000
-default CONFIG_IO_BASE=CONFIG_ISA_IO_BASE
-
-##
-## HACK ALERT: the UART0 registers are not in the PCI I/O address space
-## but both IDE and UART use the same routines for I/O (inb/outb). To get 
-## around this we set TTYSO_BASE to the difference between the two.
-##
-default CONFIG_TTYS0_BASE=0xef600300-CONFIG_ISA_IO_BASE
-
-## Enable PPC405 instructions
-default CONFIG_CPU_OPT="-mcpu=405"
-#default CONFIG_CPU_OPT=""
-default CONFIG_ARCH_X86=0
-
-## Use stage 1 initialization code
-default CONFIG_USE_INIT=1
-
-## Use chip configuration
-default CONFIG_CHIP_CONFIGURE=1
-
-## We don't use compressed image
-default CONFIG_COMPRESS=0
-
-## Turn off POST codes
-default CONFIG_NO_POST=1
-
-## Enable serial console
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_CONSOLE_SERIAL8250=1
-# Divisor of 69 == 9600 baud due to weird clocking
-default CONFIG_TTYS0_DIV=69
-default CONFIG_TTYS0_BAUD=9600
-
-## Boot linux from IDE
-default CONFIG_IDE=1
-default CONFIG_FS_PAYLOAD=1
-default CONFIG_FS_EXT2=1
-default CONFIG_FS_ISO9660=1
-default CONFIG_FS_FAT=1
-default CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
-
-default CONFIG_ROM_SIZE=1048576
-default CONFIG_ROM_IMAGE_SIZE=160*1024
-
-## Board has fixed size RAM
-default CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
-
-## Coreboot C code runs at this location in RAM
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Use a 64K stack
-##
-default CONFIG_STACK_SIZE=0x10000
-
-##
-## Use a 64K heap
-##
-default CONFIG_HEAP_SIZE=0x10000
-
-##
-## System clock
-##
-default CONFIG_SYS_CLK_FREQ=33
-
-##
-default CONFIG_ROMBASE=0xfff00000
-
-## Reset vector address
-default CONFIG_RESET=0xfffffffc
-
-## Exception vectors
-default CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100
-
-## coreboot ROM start address
-default CONFIG_ROMSTART=0xfff03000
-
-## coreboot C code runs at this location in RAM
-default CONFIG_RAMBASE=0x00100000
-
-### End Options.lb
-#
-# CBFS
-#
-#
-default CONFIG_CBFS=1
-end
diff --git a/src/mainboard/embeddedplanet/ep405pc/devicetree.cb b/src/mainboard/embeddedplanet/ep405pc/devicetree.cb
deleted file mode 100644
index b6f5329f53..0000000000
--- a/src/mainboard/embeddedplanet/ep405pc/devicetree.cb
+++ /dev/null
@@ -1,17 +0,0 @@
-chip cpu/ppc/ppc4xx 
-	device pci_domain 0 on
-		device pci 0.0 on end
-		chip southbridge/winbond/w83c553 
-			device pci 9.0 on end # ISA bridge
-			device pci 9.1 on end # IDE contoller
-		end
-		device pci e.0 on end
-	end
-end
-	
-##
-## Build the objects we have code for in this directory.
-##
-
-addaction coreboot.a "$(CONFIG_CROSS_COMPILE)ranlib coreboot.a"
-makedefine CFLAGS += -msoft-float
diff --git a/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg b/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg
deleted file mode 100755
index 305245d751..0000000000
--- a/src/mainboard/embeddedplanet/ep405pc/ep405pc.cfg
+++ /dev/null
@@ -1,89 +0,0 @@
-; bdiGDB configuration file for the Embedded Planet EP405PC
-; ---------------------------------------------------------
-;
-[INIT]
-; init core register
-WSPR	954	0x00000000      ;DCWR: Disable data cache write-thru
-WSPR	1018	0x00000000	;DCCR: Disable data cache
-WSPR	1019	0x00000000	;ICCR: Disable instruction cache
-WSPR	981	0x00000000	;EVPR: Exception Vector Table @0x00000000
-
-; Setup SDRAM Controller
-WDCR	16	0x00000080	;Select SDRAM0_TR
-WDCR	17	0x010E8016	;TR: SDRAM Timing Register
-WDCR	16	0x00000040	;Select SDRAM0_B0CR
-WDCR	17	0x00084001	;Select bank 0
-WDCR	16	0x00000030	;Select SDRAM0_RTR
-WDCR	17	0x08080000	;RTR: Refresh Timing Register
-WDCR	16	0x00000094	;Select SDRAM0_ECCCFG
-WDCR	17	0x00000000	;ECC: Disabled
-WDCR	16	0x00000034	;Select SDRAM0_PMIT
-WDCR	17	0x0F000000	;PMIT: Power Management Idle Timer
-DELAY	1			;Wait for SDRAM powerup
-WDCR	16	0x00000020	;Select SDRAM0_CFG
-WDCR	17	0x80C00000	;CFG: Enable
-
-; MMU
-WM32	0xf0	0x00000000	;invalidate page table base
-
-; EBC
-WDCR	0x12	0x00000004	;Select EBC0_B4CR
-WDCR	0x13	0xF4058000	;Set NVRTC/BCSR
-WDCR	0x12	0x00000014	;Select EBC0_B4AP
-WDCR	0x13	0x04050000	;Set NVRTC/BCSR timing
-WM8	0xF4000003    0x20	;Enable UART0
-WM8	0xF4000009    0x07	;LED
-DELAY 500
-WM8	0xF4000009    0x0b	;LED
-DELAY 500
-WM8	0xF4000009    0x0d	;LED
-DELAY 500
-WM8	0xF4000009    0x0e	;LED
-DELAY 500
-
-[TARGET]
-JTAGCLOCK   0                   ;use 16 MHz JTAG clock
-CPUTYPE     405 		;the used target CPU type
-BDIMODE     AGENT   	        ;the BDI working mode (LOADONLY | AGENT)
-;WAKEUP      3000                ;wakeup time after reset
-BREAKMODE   HARD      	        ;SOFT or HARD, HARD uses PPC hardware breakpoint
-STEPMODE    JTAG                ;JTAG or HWBP, HWPB uses one or two hardware breakpoints
-VECTOR      CATCH               ;catch unhandled exceptions
-MMU         XLAT 0xC0000000     ;enable virtual address mode
-PTBASE      0x000000f0          ;address where kernel/user stores pointer to page table
-SIO         2002 9600              ;TCP port for serial IO
-;SIO         2002 115200              ;TCP port for serial IO
-
-;REGLIST     SPR                 ;select register to transfer to GDB
-;REGLIST     ALL                 ;select register to transfer to GDB
-;SCANPRED    2 2                 ;JTAG devices connected before PPC400
-;SCANSUCC    3 3                 ;JTAG devices connected after PPC400
-
-[HOST]
-IP          10.0.1.2
-FORMAT      ELF
-FILE        coreboot.elf
-;START       0x200000
-LOAD        MANUAL              ;load code MANUAL or AUTO after reset
-DEBUGPORT   2001
-DUMP        dump.bin            ;Linux: dump.bin must already exist and public writable
-
-[FLASH]
-WORKSPACE   0x00004000  ;workspace in target RAM for fast programming algorithm
-CHIPTYPE    AM29BX16       ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16)
-CHIPSIZE    0x400000    ;The size of one flash chip in bytes (e.g. AM29F040 = 0x80000)
-BUSWIDTH    16          ;The width of the flash memory bus in bits (8 | 16 | 32)
-ERASE       0xFFF80000  ;erase sector 0 of flash in U7 (AM29F040)
-ERASE       0xFFF90000  ;erase sector 1 of flash
-ERASE       0xFFFA0000  ;erase sector 2 of flash
-ERASE       0xFFFB0000  ;erase sector 3 of flash
-ERASE       0xFFFC0000  ;erase sector 4 of flash
-ERASE       0xFFFD0000  ;erase sector 5 of flash
-ERASE       0xFFFE0000  ;erase sector 6 of flash
-ERASE       0xFFFF0000  ;erase sector 7 of flash
-
-[REGS]
-IDCR1	0x010	0x011	;MEMCFGADR and MEMCFGDATA
-IDCR2	0x012	0x013	;EBCCFGADR and EBCCFGDATA
-IDCR3	0x014	0x015	;KIAR and KIDR
-FILE    reg405gp.def
diff --git a/src/mainboard/embeddedplanet/ep405pc/init.c b/src/mainboard/embeddedplanet/ep405pc/init.c
deleted file mode 100644
index 6148d89c4a..0000000000
--- a/src/mainboard/embeddedplanet/ep405pc/init.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2003, Greg Watson <gwatson@lanl.gov>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-/*
- * Do very early board initialization:
- *
- * - Configure External Bus (EBC)
- * - Setup Flash
- * - Setup NVRTC
- * - Setup Board Control and Status Registers (BCSR)
- * - Enable UART0 for debugging
- */
-
-#include <ppc_asm.tmpl>
-#include <ppc.h>
-#include <ppc4xx.h>
-#include <arch/io.h>
-#include <timer.h>
-
-void
-board_init(void)
-{
-	/*
-	 * Configure Inerrupt Controller
-	 */
-        mtdcr(uicsr, 0xFFFFFFFF);      /* clear all ints */
-        mtdcr(uicer, 0x00000000);      /* disable all ints */
-        mtdcr(uiccr, 0x00000000);      /* set all to be non-critical */
-        mtdcr(uicpr, 0xFFFFFF80);      /* set int polarities */
-        mtdcr(uictr, 0x10000000);      /* set int trigger levels */
-        mtdcr(uicvcr, 0x00000001);     /* set vect base=0,INT0 highest pri */
-        mtdcr(uicsr, 0xFFFFFFFF);      /* clear all ints */
-
-	/*
-	 * Configure FLASH
-	 */
-	mtebc(pb0cr, 0xFC0DC000);
-	mtebc(pb0ap, 0x02000000);
-
-	/*
-	 * Configure NVTRC/BCSR
-	 */
-	mtebc(pb4cr, 0xF4058000);
-	mtebc(pb4ap, 0x04050000);
-	
-	/*
-	 * Board Control and Status Register (BCSR) setup
-	 */
-
-	/*
-	 * BCSR1 - PCI Control
-	 */
-	out_8((unsigned char *)0xF4000001, 0x80);
-
-	/*
-	 * BCSR2 - FLASH, NVRAM and POR Control
-	 */
-	out_8((unsigned char *)0xF4000002, 0x9C);
-
-	/*
-	 * BCSR3 - FENET and UART
-	 */
-	out_8((unsigned char *)0xF4000003, 0xf0);
-
-	/*
-	 * BCSR4 - PCI Status and Masking
-	 */
-	out_8((unsigned char *)0xF4000004, 0x00);
-
-	/*
-	 * BCSR5 - XIRQ Select
-	 */
-	out_8((unsigned char *)0xF4000005, 0x00);
-
-	/*
-	 * BCSR6 - XIRQ Routing
-	 */
-	out_8((unsigned char *)0xF4000006, 0x07);
-
-	/*
-	 * Cycle LEDs to show something is happening...
-	 */
-	out_8((unsigned char *)0xF4000009, 0x07);
-	udelay(100000);
-	out_8((unsigned char *)0xF4000009, 0x0B);
-	udelay(100000);
-	out_8((unsigned char *)0xF4000009, 0x0D);
-	udelay(100000);
-	out_8((unsigned char *)0xF4000009, 0x0E);
-}
-
-void
-board_init2(void)
-{
-}
diff --git a/targets/embeddedplanet/ep405pc/Config.lb b/targets/embeddedplanet/ep405pc/Config.lb
deleted file mode 100644
index 820a38506a..0000000000
--- a/targets/embeddedplanet/ep405pc/Config.lb
+++ /dev/null
@@ -1,81 +0,0 @@
-# Config file for Embedded Planet EP405PC board
-# This will make a target directory of ./ep405pc
-
-target ep405pc
-mainboard embeddedplanet/ep405pc
-
-romimage "fallback"
-        ## Enable PPC405 instructions
-        option CONFIG_CPU_OPT="-mcpu=405"
-
-        ## use a cross compiler
-        #option CONFIG_CROSS_COMPILE="powerpc-ibm-eabi-"
-
-        ## Use stage 1 initialization code
-        option CONFIG_USE_INIT=1
-
-        ## Use chip configuration
-        option CONFIG_CHIP_CONFIGURE=1
-
-        ## We don't use compressed image
-        option CONFIG_COMPRESS=0
-
-        ## Turn off POST codes
-        option CONFIG_NO_POST=1
-
-        ## Enable serial console
-        option CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-        option CONFIG_CONSOLE_SERIAL8250=1
-        # Divisor of 69 == 9600 baud due to weird clocking
-        option CONFIG_TTYS0_DIV=69
-        option CONFIG_TTYS0_BAUD=9600
-
-        ## Boot linux from IDE
-        option CONFIG_IDE=1
-        option CONFIG_FS_PAYLOAD=1
-        option CONFIG_FS_EXT2=1
-        option CONFIG_FS_ISO9660=1
-        option CONFIG_FS_FAT=1
-        option CONFIG_AUTOBOOT_CMDLINE="hda1:/vmlinuz"
-
-        option CONFIG_ROM_SIZE=1024*1024
-
-        ## Board has fixed size RAM
-        option CONFIG_EMBEDDED_RAM_SIZE=64*1024*1024
-
-        ## Coreboot C code runs at this location in RAM
-        option CONFIG_RAMBASE=0x00100000
-
-        ##
-        ## Use a 64K stack
-        ##
-        option CONFIG_STACK_SIZE=0x10000
-
-        ##
-        ## Use a 64K heap
-        ##
-        option CONFIG_HEAP_SIZE=0x10000
-
-        ##
-        ## System clock
-        ##
-        option CONFIG_SYS_CLK_FREQ=33
-
-	##
-	option CONFIG_ROMBASE=0xfff00000
-
-	## Reset vector address
-	option CONFIG_RESET=0xfffffffc
-
-	## Exception vectors
-	option CONFIG_EXCEPTION_VECTORS=CONFIG_ROMBASE+0x100
-
-	## coreboot ROM start address
-	option CONFIG_ROMSTART=0xfff03000
-
-	## coreboot C code runs at this location in RAM
-	option CONFIG_RAMBASE=0x00100000
-
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"