mb/intel/dcp847ske: Make devicetree prettier

Align contents and fix some redundant comments.

Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>

1 files changed, 28 insertions, 27 deletions

diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index 6ed7c03120..b62c5dffd1 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -28,36 +28,37 @@ chip northbridge/intel/sandybridge
 		end
 	end
 	device domain 0x0 on
-		device pci 00.0 on end # Host bridge Host bridge
-		device pci 01.0 off end # PCIe Bridge for discrete graphics
-		device pci 02.0 on end # Internal graphics VGA controller
+		device pci 00.0 on  end	# Host bridge
+		device pci 01.0 off end	# PCIe Bridge for discrete graphics
+		device pci 02.0 on  end	# Internal graphics VGA controller
+
 		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 			register "c2_latency" = "0x0065"
 			register "sata_port_map" = "0x1"
 			register "spi_lvscc" = "0x2005"
 			register "spi_uvscc" = "0x2005"
 
-			register "gen1_dec" = "0x00fc0a01"  # SuperIO @0xa00-0xaff
+			register "gen1_dec" = "0x00fc0a01"	# SuperIO @0xa00-0xaff
 
-			device pci 14.0 off end # USB xHCI
-			device pci 16.0 on end # Management Engine Interface 1
-			device pci 16.1 off end # Management Engine Interface 2
-			device pci 16.2 off end # Management Engine IDE-R
-			device pci 16.3 off end # Management Engine KT
-			device pci 19.0 on end # Intel Gigabit Ethernet
-			device pci 1a.0 off end # USB2 EHCI #2
-			device pci 1b.0 on end # High Definition Audio Audio controller
-			device pci 1c.0 on end # PCIe Port #1 (unused)
-			device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA)
-			device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe)
-			device pci 1c.3 off end # PCIe Port #4
-			device pci 1c.4 off end # PCIe Port #5
-			device pci 1c.5 off end # PCIe Port #6
-			device pci 1c.6 off end # PCIe Port #7
-			device pci 1c.7 off end # PCIe Port #8
-			device pci 1d.0 on end # USB2 EHCI #1
-			device pci 1e.0 off end # PCI bridge
-			device pci 1f.0 on # LPC bridge PCI-LPC bridge
+			device pci 14.0 off end	# USB xHCI
+			device pci 16.0 on  end	# Management Engine Interface 1
+			device pci 16.1 off end	# Management Engine Interface 2
+			device pci 16.2 off end	# Management Engine IDE-R
+			device pci 16.3 off end	# Management Engine KT
+			device pci 19.0 on  end	# Intel Gigabit Ethernet
+			device pci 1a.0 off end	# USB2 EHCI #2
+			device pci 1b.0 on  end	# HD Audio controller
+			device pci 1c.0 on  end	# PCIe Port #1 (unused)
+			device pci 1c.1 on  end	# PCIe Port #2 (full-length mPCIe/mSATA)
+			device pci 1c.2 on  end	# PCIe Port #3 (half-length mPCIe)
+			device pci 1c.3 off end	# PCIe Port #4
+			device pci 1c.4 off end	# PCIe Port #5
+			device pci 1c.5 off end	# PCIe Port #6
+			device pci 1c.6 off end	# PCIe Port #7
+			device pci 1c.7 off end	# PCIe Port #8
+			device pci 1d.0 on  end	# USB2 EHCI #1
+			device pci 1e.0 off end	# PCI bridge
+			device pci 1f.0 on	# LPC bridge
 				chip superio/nuvoton/nct6776
 					device pnp 4e.0 off end		# Floppy
 					device pnp 4e.1 off end		# Parallel port
@@ -98,10 +99,10 @@ chip northbridge/intel/sandybridge
 					device pnp 4e.17 off end	# GPIOA
 				end
 			end
-			device pci 1f.2 on end # SATA Controller 1
-			device pci 1f.3 on end # SMBus
-			device pci 1f.5 off end # SATA Controller 2
-			device pci 1f.6 off end # Thermal
+			device pci 1f.2 on  end	# SATA Controller 1
+			device pci 1f.3 on  end	# SMBus
+			device pci 1f.5 off end	# SATA Controller 2
+			device pci 1f.6 off end	# Thermal
 		end
 	end
 end