soc/mediatek: improve ca53 frequency change procedure

To change frequency, the SOC PLL team suggests procedure below:
First, we need to enable the intermediate clock and
switch the ca53 clock source to the intermediate clock.
Second, disable the armpll_ll clock output.
Third, raise armpll_ll frequency and enable the clock output.
The last, switch the ca53 clock source back to armpll_ll and
disable the intermediate clock.

BUG=b:154451241
BRANCH=jacuzzi
TEST=Boots correctly on Jacuzzi.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ib9556ba340da272fb62588f45851c93373cfa919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41077
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

2 files changed, 23 insertions, 0 deletions

diff --git a/src/soc/mediatek/mt8183/include/soc/pll.h b/src/soc/mediatek/mt8183/include/soc/pll.h
index 3fa7366942..3aa77c9f3b 100644
--- a/src/soc/mediatek/mt8183/include/soc/pll.h
+++ b/src/soc/mediatek/mt8183/include/soc/pll.h
@@ -217,6 +217,7 @@ enum {
 
 	MUX_MASK = 0x3 << 9,
 	MUX_SRC_ARMPLL = 0x1 << 9,
+	MUX_SRC_DIV_PLL1 = 0x2 << 9,
 };
 
 enum {
diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c
index 39dfa264e3..dedd59d4f2 100644
--- a/src/soc/mediatek/mt8183/pll.c
+++ b/src/soc/mediatek/mt8183/pll.c
@@ -365,5 +365,27 @@ void mt_pll_init(void)
 
 void mt_pll_raise_ca53_freq(u32 freq)
 {
+	/* enable [4] intermediate clock armpll_divider_pll1_ck */
+	setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
+
+	/* switch ca53 clock source to intermediate clock */
+	clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
+		MUX_SRC_DIV_PLL1);
+
+	/* disable armpll_ll frequency output */
+	clrbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+
+	/* raise armpll_ll frequency */
 	pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq);
+
+	/* enable armpll_ll frequency output */
+	setbits32(plls[APMIXED_ARMPLL_LL].reg, PLL_EN);
+	udelay(PLL_EN_DELAY);
+
+	/* switch ca53 clock source back to armpll_ll */
+	clrsetbits32(&mt8183_mcucfg->mp0_pll_divider_cfg, MUX_MASK,
+		MUX_SRC_ARMPLL);
+
+	/* disable [4] intermediate clock armpll_divider_pll1_ck */
+	clrbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 4);
 }